Hello,
On my design the clock drivers generated by clock buffer and it takes 25mS power up to clock valid on its output.
According to power sequence section 7.3.1.2 (SPRS691E): IO-Before-Core power sequencing it is written:
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
my Q:
is that OKay enabling CVDD, wait for stabilization -> Enable Clocks -> wait 26mS (Stabilization Time) -> Enable CVDD1 ->....
in other words, is it OKay perform power up sequence steps on page 126 in the following order: 1->2a->2b->3b->wait 26mS-> 3a (power CVDD1)
what should be the risks in terms of currents between the rails if any?
thanks,
Erez.
