I am trying to understand the connection of the CE signals in a 8 - 16M x8 x8 bank setup on a C6678 as described in table 28 of SPRABI1. This table shows that CE0 goes to the lower 4 DDR chips, and that CE1 goes to the upper 4 DDR chips, so it looks like when you enable one or the other CE line you will only get to use half of the 64 bit wide bus. I am trying to understand why one would want to hook up the DDR3 bus this way, since based on SPRUGV8 section 2.5 table 2-4 and 2-5 it looks like the CE selection is in the middle of the logical address, thus it appears you would have a wide internal addressing stride between each half of the 64 bit bus. The problem with this is that if you were to access a lot of data sequentially, it seems like you would not be getting your full bandwidth potential on the 64 bit wide DDR3 bus.
Is my understanding of the CE connection accurate, and if so why do we recommend connecting this way? Is there a better way to hook up the CE signals to maximize the bus bandwidth available?
