Part Number: TDA4VM
Hello, we are developing a custom platform with a main TDA4 SoC.
Processor SDK version: 06_02_00 (we are planing to upgrade to 7_01_00 in the next phase of development)
We are currently stuck trying to enable PCIe on SerDes3 on lane1.
As per our design SerDes3 lane0 goes to USB3 hub and lane1 goes to PCIe controller.
We are aware that PSDK version 6.02 does not support concurrent configuration of SerDes to both USB and PCIe, so we are trying do configure SerDes3 to have only PCIe on lane1 for bring-up purposes.
Since we fail to do so, we wonder if it is possible at all to have PCIe configured on SerDes lane1, or it must be on lane0?
We did not find any restrictions in technical documentation, and we know that on EVM board one SerDes is configured to have only PCIe on lane0.
Can you help us to clear this issue up?
Regards
Uros