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C6A8168 DDR2/3 Memory Configuration

Ockie Van Schalkwyk
Intellectual 420 points

I am working on a new design that will use the C6A8168 and I am currently figuring out how the dual DDR2/3 memory controllers work.

The datasheet (Par. 8.17) refers one to the Technical Reference Manual ("For details on the DDR2/3 Memory Controller, see the DDR2/3 Memory Controller chapter in the TMS320C6A8x Integra DSP+ARM Processors Technical Reference Manual (literature number SPRUGX9)"); only, I don't see any "DDR2/3 Memory Controller chapter" in that document. Am I missing something here?

The most pressing question I have at this time is whether the two DDR memory banks can be accessed by the ARM and DSP in parallel (ie, can the ARM access DDR[0] and the DSP access DDR[1], at the same time, without blocking each other)?

Thanx.

  • 0
    TI__Mastermind 25055 points

    Hello,

    The DDR section of the TRM is being worked on and should be added soon.

     As for your other question, here is how the connections work:

    • Everything talks to the DMM and sees up to 2 GBytes of memory space
    • DMM talks to the two DDR interfaces
    • DMM has sections defined which are basically memory ranges
    • Each range can have properties that include:
      • Mapped to DDR0 only
      • Mapped to DDR1 only
      • Mapped to both with interleaving, which can be variable size.

    So in summary, even though it might not be the recomended way of doing it (since you can't make use of the interleaving feature), the DSP could be mapped to DDR0 only and the ARM to DDR1 only.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Intellectual 420 points

    Hi Marc

    Thanks for your reply.

    Please elaborate a bit on the operation of the DMM. Is the available memory bandwidth shared in the case of interleaved or separately mapped (DDR0->DSP, DDR1->ARM) memory, or can both DDR0 and DDR1 be accessed simultaneously at the peak bus speed of 1600 MHz by the DSP and ARM cores respectively?

    Regards
    Ockie 

  • 0 in reply to Ockie Van Schalkwyk
    TI__Mastermind 25055 points

    Ockie,

    If interleaving is used, then it can effectively double the DDR bandwidth when both interfaces are used simultaneously.  If they are separately mapped than each will operate separately at the standard data rates.

    Regards,
    Marc