• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 444 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP-L138: DDR2 Data Read Overshoots

Francisco Lozada
Prodigy 20 points

Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138,

We're interfacing to the MT47H64M16NF, no serial termination resistors, DVDD = 1.8V (no termination due to space constraints). We see 2.44V of overshoot for about 21% of the period and slight undershoot that does not go below 1.8V - 0.3V. We also see negative overshoot (below 0V) to -460mV for about 17% of the period. This is a Hyperlynx simulation using sprm378c/omapl138_zwt.ibs, fast-strong case and the DDR is set to "DQ_HALF_800" drive. We noticed this ibis has no input model so we used the Output Tri-State (DQ_NOSR0_NOTERM_0).
1. Is this voltage waveform within the absolute maximum limits?
2. Is the Absolute Maximum Clamp Current at +/-20mA measured at DVDD + 0.3V? Is our voltage waveform going to result in a clamp current of >20mA when it drifts above DVDD+0.3V?
3. Ibis model POWER Clamp is ~3mA at -540mV (1.9V - 2.44V). We see this current in the simulation, after the rising edge dv/dt spike. Why is this current much less than the 20mA above?

  • 0
    TI__Genius 9190 points

    Hello, these IBIS models are not good for simulating the DDR interface.  I would say to choose the High-Z for Input, but I still don't think it will look right in the modeling tool.  For the OMAP-L138 we guarantee timing will be met if you adhere to the DDR routing guidelines in the data sheet section 6.11.3.  

    please also reference the DDR application note: https://www.ti.com/lit/pdf/spraav0

    And the schematic review guidelines in section 2.4.4.3: https://www.ti.com/lit/pdf/sprack9

  • 0 in reply to Jeff Culverhouse
    TI__Genius 9190 points

    Hello, after looking at this further and talking to several colleagues, t we would like to see if you can simulate with series terminations populated to see if it helps the issue. 

    Because the OMAP-L138 is the input, we suspect that the IBIS model for the Micron device may be incorrect.  Also, please make sure you are choosing half drive strength for this device.  

    https://processors.wiki.ti.com/index.php/DDR_Interface_Drive_Strength

    Is there any chance we could get your file to so we can work with it?  

  • 0 in reply to Jeff Culverhouse
    Prodigy 20 points

    Hello and thanks for your responses.
    After spending some time simulating with different scenarios, it appears that the ibis model for the Micron device is causing the overshoots. We replaced the model with an older version that produced much less overshoot at the fast-strong corner case, half drive strength (555mV from 1.9V versus 274mV from 1.9V).

    To answer your question yes, we have simulated with series terminations and it helps, but we are looking into avoiding them due to space limitations.

    We are now looking at the rules based approach that you suggested and have two questions:

    1- Review guidelines in section 2.4.4.3 (https://www.ti.com/lit/pdf/sprack9) the following rule:

    For DQS and D net classes:  Skew between the two classes should not exceed 25 mil.

    appears to conflict with datasheet Table 5-37: DQS and D Routing Specification No. 3: D to DQS  Skew Length Mismatch of 100 mils maximum.

    Do these requirements refer to the same thing, using different numbers? Which one should we follow?

    2- Can you provide DDR2 controller timing models (hyperlynx ddr2_ctl.v) or a list of the following: tCKAC, tCKCTL, tCKDQS, tDQSDQ, tDQDQS, tDS, tDH?

    Thanks!