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AM5728: Help with Embedded SDIO Device enumeration with MMC1 Host controller

Someshwar DK
Intellectual 330 points
Part Number: AM5728
Other Parts Discussed in Thread: SYSCONFIG, TXS0206A

We are working on a custom board with AM5728 chipset and MMC1 Host controller is connected to an Embedded SDIO device with I/O-only support with no internal memory.

The Host Controller is programmed and controlled from DSP1 and we are using TI provided LLD driver routines. We have modified the TI Example application to send appropriate SDIO commands to enumerate our Embedded SDIO device. We are enumerating the SDIO device by following the I/O Aware sequence on the Host controller and so far, we were able to reach till below point,

Passes => CMD5 with expected response [0] 0x10ffff00, [1] 0x0, [2] 0x0, [3] 0x0

Passes => Polling of CMD5 till I/O ready bit gets set

Passes => CMD3 to request RCA and we receive valid RCA of 0x1

After this, sending of CMD7 for Card select with RCA=0x1 (as received from CMD3) is timing out

When we probe the MMC1_CMD and MMC1_CLK lines, we are seeing that after sending CMD7, Host controller does not see any response for 64 MMC clock cycles. According to MMCHS.CTO, it states that if a response is not received within 64 clocks Host controller raises the CTO event.

The same Embedded SDIO Device has been used on a different board connected to a Cypress based SDIO host controller and the enumeration goes through properly on that board design. On this new board design, the same SDIO Device is failing at CMD7 with Host controller not receiving any response.

Below points are similar between the two setups,

1. MMC Clock frequency is at 400KHz during these initial enumeration commands

2. CMD5/CMD3 sent before CMD7 are matching in both Command sent and Response received

3. Same Embedded SDIO Device is present on both the boards

I see two main differences when I compare the non-working case on AM5728 with the working Cypress board,

1. MMC Clock line when probed is continuous in working case and is not gated by Host controller activity. I configured the MMCHS_SYSCONFIG[0].AUTOIDLE=0x0 to get a free-running clock, but when probed, we still see the clock getting gated with MMC Command pin activity. We are reading MMCHS_SYSCONFIG=0x00001308 from the Host controller. What is the right programming needed for ungated/free-running MMC clock?

2. The non-working case has a TI level translator, TXS0206A, connected from Host controller (3.3V) to Embedded SDIO working at 1.8V. In working case, this level translator is not present. For now, I am assuming with CMD3/CMD5 working properly at 400KHz, CMD7 should also have responded properly

Below is the waveform seen with non-working case,

Below is the capture seen with working case,

Any inputs on solving this issue will be helpful.

thanks--

Somesh

  • 0
    Intellectual 330 points

    I got the answer to one part of my query for configuring the Host controller to get ungated MMC Clock.

    Below register fields were programmed and I see continuous clock of 400KHz on MMC Clock line.

    > MMCHS_CON.CLKEXTFREE=0x1

    > MMCHS_SYSCTL.CEN=0x1

    > MMCHS_SYSCONFIG.AUTOIDLE=0x0

    This reduces one more variable between the working and non-working setup. The CMD7 is still timing out with this update and only difference now is the level translator between Host controller and our Embedded SDIO device.

    One additional query, how should we configure the Host controller to work with 1.8V only instead of 3.3V? I am looking for the possibility of eliminating the Level translator as well.

    thanks--

    Somesh

  • 0 in reply to Someshwar DK
    TI__Genius 10180 points

    Somesh,

    Did you set S18R in CMD5?  Moreover, what was the card status in the CMD3 RSP?  If you can take a scope capture of the CLK and CMD signals after level translator to show CMD7, that will be beneficial as well.

    Which MMC module are you using?  Some of the register changes you will need to operate in 1.8V include...

    MMCHS_AC12[19] V1V8_SIGEN = 0x1 (to indicate 1.8 V operation)

    MMCHS_HCTL[11:9] SDVS = 0x5 (to select 1.8 V SD bus voltage)

    MMCHS_CAPA register should also have [26] VS18 set to 1 to indicate voltage support for 1.8V.  Also pay special attention to MMCHS_AC12[18:16] UHSMS for the correct mode setting.

    Best Regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Intellectual 330 points

    Hi Shiou Mei,

    I have answered your queries below,

    > S18R bit is not set in CMD5, if I set that bit in CMD5 then I see a response timeout on CMD5 itself

    > For CMD3, card status is 0

    > We are using MMC1 Host controller instance (0x4809C000) and this is connected to our Embedded SDIO Device

    MMC2 Host controller @ 0x480B4000 is also in use and connected to eMMC and this works fine


    Below is the log capture from my DSP program. I am using MMCSD_v1_transfer() routine for the transfer of CMD5/CMD3/CMD7 in polling mode.

    [ 0.000] [0] MMC@0x4809c000
    [ 0.000] Custom MMCSD_v1_open:748
    [ 0.000] Disabled Interrupts
    [ 0.000] EDMA Disabled
    [ 0.000] SDIO_CARD_EMMC
    [ 0.000] clockActivity:3, standbyMode:1, idleMode:1, enableWakeup:0, enableAutoIdle:0
    [ 0.000] --IN--
    [ 0.000] CMD:5, flags:0x200, arg:0x0
    [ 0.001] [Ret:0] CMD5 Response: [0] 0x10ffff00, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.001] --OUT--
    [ 0.001] CMD5 passed
    [ 0.001] Waiting till Card is ready (CMD5 Response I/O ready should be set)
    [ 0.001] --IN--
    [ 0.001] CMD:5, flags:0x200, arg:0x0
    [ 0.001] [Ret:0] CMD5 Response: [0] 0x90ffff00, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.001] --OUT--
    [ 0.001] [0/0xFFFF] Memory is absent
    [ 0.002] IO Initialization passed
    [ 0.002] --IN--
    [ 0.002] CMD:3, flags:0x200, arg:0x0
    [ 0.002] [Ret:0] CMD3 Response: [0] 0x10000, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.002] --OUT--
    [ 0.002] Attempt-0 => RCA=0x1
    [ 0.002] Final RCA received as 0x1
    [ 0.002] --IN--
    [ 0.002] CMD:7, flags:0x200, arg:0x10000
    [ 0.003] Response Timeout Error (0x00010000) occurred in execution of command
    [ 0.003] MMCSD:(@4809c000) Command Execution timed out
    [ 0.003] [Ret:-1] CMD7 Response: [0] 0x10000, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.003] --OUT--
    [ 0.003] [0] Card selection failed
    [ 0.003] Card selection failed

    Below is the register dump after CMD7 has timed out,

    MMCHS_HL_REV : 0x40200303
    MMCHS_HL_HWINFO : 0x0000004b
    MMCHS_HL_SYSCONFIG : 0x00000014
    MMCHS_SYSCONFIG : 0x00001308
    MMCHS_SYSSTATUS : 0x00000001
    MMCHS_CSRE : 0x00000000
    MMCHS_SYSTEST : 0x00008000
    MMCHS_CON : 0x00010600
    MMCHS_PWCNT : 0x00000000
    MMCHS_DLL : 0x80000000
    MMCHS_SDMASA : 0x00000000
    MMCHS_BLK : 0x00000000
    MMCHS_ARG : 0x00010000
    MMCHS_CMD : 0x07020000
    MMCHS_RSP10 : 0x00010000
    MMCHS_RSP32 : 0x00000000
    MMCHS_RSP54 : 0x00000000
    MMCHS_RSP76 : 0x00000000
    MMCHS_DATA : 0x00000000
    MMCHS_PSTATE : 0x00000001
    MMCHS_HCTL : 0x00000f00
    MMCHS_SYSCTL : 0x00007807
    MMCHS_STAT : 0x00000000
    MMCHS_IE : 0x00010001
    MMCHS_ISE : 0x00000000
    MMCHS_AC12 : 0x00000000
    MMCHS_CAPA : 0x21e90080
    MMCHS_CAPA2 : 0x00000f77
    MMCHS_CUR_CAPA : 0x00000000
    MMCHS_FE : 0x00000000
    MMCHS_ADMAES : 0x00000000
    MMCHS_ADMASAL : 0x00000000
    MMCHS_PVINITSD : 0x000401e0
    MMCHS_PVHSSDR12 : 0x00040002
    MMCHS_PVSDR25SDR50 : 0x00010002
    MMCHS_PVSDR104DDR50 : 0x00020000
    MMCHS_REV : 0x33020000

    Below is the CRO capture of MMC1_CMD and MMC1_CLK lines for CMD7 after the level translator (1.8V),

    Our Board design team say that removing the Level translator from the board may take some time and the integrity of the lines will need to be checked after that.

    The level translator introduces 4ns delay on each line (according to the Datasheet) and within the limit for 25MHz clocking to achieve 100Mbps throughput on data lines. For this initial communication with 400KHz, I am assuming delay with Level Translator is not an issue. I want to exhaust all options with the level translator on board before moving to the next option.

    thanks--

    Somesh

  • 0 in reply to Someshwar DK
    TI__Genius 10180 points

    Somesh,

    Based on your registers, there are some configuration updates that are needed:

    1. CMD7 has response type R1b; please set bit fields [17:16] to 0x3.  Would also recommend enabling [19] Command CRC and [20] Index check

    2. PSTATE shows DAT and CMD lines are all at 0x0.  When did you dump the registers?

    3. It will be beneficial to enable all the interrupt bits for debug purposes

    4. In the scope capture, please also probe DAT lines to check if the PSTATE register was correct, and if DAT0 is still held in busy state after CMD was transmitted.

    Best Regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Intellectual 330 points

    Hi Shiou Mei,

    We have now got our Embedded SDIO device enumerated and are able to do block-based data transfers using Polling mode enabled, ie, non-EDMA mode. We are now working towards data integrity testing and link characterization.

    Once this completes, we will work on enabling EDMA support in MMC Host controller driver. I have some queries on that as well, but the primary query of this mail chain has been addressed and I will create another related query with that question.

    Thanks for your support.

    --Somesh

  • 0 in reply to Someshwar DK
    TI__Genius 10180 points

    Somesh,

    Great to hear!  Can you summarize what modifications you made so others can benefit?

    Have a great day!

    Best Regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Intellectual 330 points

    Hi Shiou Mei,

    Some of the below listed points got the enumeration to work along with Data transfers,

    1. We isolated the AM5728 from our board and connected Cypress Host controller to confirm all connections on our SDIO Device. This setup worked out-of-box with no issues

    2. Our Embedded SDIO Device expected commands to be sent in a specific order starting from CMD5. Below is the reference log of commands till the first CMD52 and is generic for SDIO devices. I believe proper voltage was not selected during one of the CMD5 polling and this was causing CMD7 to fail. Please note: We are still working with interrupts disabled and in non-EDMA mode. I will work on enabling this next. As TI DSP SD/MMC stack does not support SDIO enumeration, we had to enhance the stack ourselves to achieve this.

    ---

    [ 0.000] [t=0x00031227] xdc.runtime.Main: MMC@0x4809c000
    [ 0.000] [t=0x0003980c] xdc.runtime.Main: Disabled Interrupts
    [ 0.000] [t=0x00042570] xdc.runtime.Main: EDMA Disabled
    [ 0.000] [t=0x000493aa] xdc.runtime.Main: SDIO_CARD_EMMC
    [ 0.000] [t=0x0004ff1a] xdc.runtime.Main: clockActivity:3, standbyMode:1, idleMode:1, enableWakeup:0, enableAutoIdle:0
    [ 0.000] [t=0x0007c434] xdc.runtime.Main: Host init is completed
    [ 0.000] [t=0x00083e1a] xdc.runtime.Main: --IN--
    [ 0.000] [t=0x00089925] xdc.runtime.Main: CMD:5, flags:0x200, arg:0x0
    [ 0.001] [t=0x000be398] xdc.runtime.Main: [Ret:0] CMD5 Response: [0] 0x10ffff00, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.001] [t=0x000cd3d7] xdc.runtime.Main: --OUT--
    [ 0.001] [t=0x000d46d6] xdc.runtime.Main: CMD5 passed
    [ 0.001] [t=0x000dc05c] xdc.runtime.Main: Waiting till Card is ready (CMD5 Response I/O ready should be set)
    [ 0.001] [t=0x000e950e] xdc.runtime.Main: --IN--
    [ 0.001] [t=0x000f036c] xdc.runtime.Main: CMD:5, flags:0x200, arg:0xffff00
    [ 0.001] [t=0x00124b21] xdc.runtime.Main: [Ret:0] CMD5 Response: [0] 0x90ffff00, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.001] [t=0x0013289a] xdc.runtime.Main: --OUT--
    [ 0.001] [t=0x00139b7e] xdc.runtime.Main: [0/0xFFFF] Memory is absent
    [ 0.001] [t=0x0014342a] xdc.runtime.Main: IO Initialization passed
    [ 0.002] [t=0x0014d36f] xdc.runtime.Main: --IN--
    [ 0.002] [t=0x001547cd] xdc.runtime.Main: CMD:3, flags:0x200, arg:0x0
    [ 0.002] [t=0x00187881] xdc.runtime.Main: [Ret:0] CMD3 Response: [0] 0x10000, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.002] [t=0x00195117] xdc.runtime.Main: --OUT--
    [ 0.002] [t=0x0019c5cc] xdc.runtime.Main: Final RCA received as 0x1
    [ 0.002] [t=0x001a5b30] xdc.runtime.Main: --IN--
    [ 0.002] [t=0x001ac9eb] xdc.runtime.Main: CMD:7, flags:0x200, arg:0x10000
    [ 0.003] [t=0x001dfc5b] xdc.runtime.Main: [Ret:0] CMD7 Response: [0] 0x1e00, [1] 0x0, [2] 0x0, [3] 0x0
    [ 0.003] [t=0x001ed4c1] xdc.runtime.Main: --OUT--
    [ 0.003] [t=0x001f4670] xdc.runtime.Main: [0] Card selection passed
    [ 0.003] [t=0x001fd86b] xdc.runtime.Main: emmc card card_select success
    [ 0.005] [t=0x00308e98] xdc.runtime.Main: Stage-1: CCCR Version:0x1, SDIO Version:0x1, SD Spec Version:0x1
    [ 0.005] [t=0x00317229] xdc.runtime.Main: Stage-1: SDR50 Support is absent
    [ 0.005] [t=0x00320b83] xdc.runtime.Main: Stage-1: SDR104 Support is absent
    [ 0.005] [t=0x0032a6d2] xdc.runtime.Main: Stage-1: DDR50 Support is absent
    [ 0.005] [t=0x00334077] xdc.runtime.Main: Stage-1: Card supports High speed Mode
    [ 0.005] [t=0x0033e48a] xdc.runtime.Main: Stage-1: Default Bus-speed 1.8V = SDR12
    [ 0.005] [t=0x00349b4e] xdc.runtime.Main: MMCSD_switch_card_speed: Setting Bus Frequency Succeeded to 50MHz
    [ 0.005] [t=0x003574cb] xdc.runtime.Main: MMCSD_switch_card_speed: All OK so far
    [ 0.005] [t=0x00367368] xdc.runtime.Main: Stage-2: Set Bus-width = 4-bit
    [ 0.005] [t=0x003716a3] xdc.runtime.Main: Stage-2: Set Bus-speed 1.8V = SDR25
    [ 0.006] [t=0x0037c79a] xdc.runtime.Main: Stage-2: Updated Block Gap interrupt 0x3

    [ 0.006] [t=0x003877d4] xdc.runtime.Main: Stage-2: Interrupt Enable Master
    [ 0.006] [t=0x0039134d] xdc.runtime.Main: Stage-2: Interrupt Enable for Function-1
    [ 0.006] [t=0x0039fd14] xdc.runtime.Main: Fetched CIS successfully => 0x452301

    ---

    3. Reading of CSA space on Func-1 has not been implemented in Silicon in our device, we had to skip reading that. This however did not affect preparing for any data transfers

    4. Reading/Writing from Func-1 has a custom sequence unique to our Device, understanding the right sequence for Data-transfers took some time

    5. With this we can now confirm 3.3V to 1.8V communication using the Level translator works fine

    Hope this info helps!

    thanks--

    Somesh