Is this the right way to give CPU priority over all EMDA towards EMIF activity?
According to TMS320C6455-6.pdf:
0182 020C EMCMDMAARBE EMC Master DMA Arbitration Control Resgiter
*(volatile int*)0x0182020c = 1<<16; // EMCMDMAARBE register gives CPU to EMIF priority 1
DMA que number registers (DMAQNUM) are set to 2 or 3 for used DMA channels
02A0 0284 Queue Priority Register QUEPRI has content:
PRIQ0 = 0, PRIQ1 = 1, PRIQ2 = 2, PRIQ3 = 3
There are 2 simultaneous DMA processes working on QUE2 and 2 simultaneous DMA processes working on QUE3