This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Original question:
Part Number: TDA4VM
dear experts:
Regard of the ePWM module demo project. it's lack of the pwm isr demo. could you provide the pwm isr demo for us?
Bye the way. can I modify the epwm frequency to 6.666Khz also generate the pwm interrupt ? the reason is that period required for the peripheral is 150us!
thanks!
Hi, Binbin:
I have tried to output 6.4KHz PWM.
And I also can get PWM interrupt.
Please check my test example.
/*
* Copyright (c) Texas Instruments Incorporated 2020
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* \file epwm_app.c
*
* \brief This file contains PWM test application which sets a particular
* duty cycle in PWMSS1 output A (EHRPWM1A) which can be verified
* through external pin probing.
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include APP_CFG_FILE
#ifdef ENABLE_EPWM_TEST
#if defined(CPU_mcu2_0)
#elif defined(CPU_mcu1_0)
#else
#error "this ePWM example only has been verified on MCU1_0 and MCU2_0"
#endif
#include <string.h>
#include <stdint.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/src/ip/epwm/V0_1/cslr_hrpwm.h>
#include <ti/csl/src/ip/epwm/V0/hw_pwmss_epwm.h>
#include <ti/csl/csl_epwm.h>
#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
#include <ti/board/board.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/src/ip/epwm/V0/csl_epwm.h>
#include <ti/csl/soc/j721e/src/cslr_soc_baseaddress.h>
#include <ti/csl/soc/j721e/src/cslr_main_ctrl_mmr.h>
#include <ti/board/src/j721e_evm/include/pinmux.h>
#include <ti/board/src/j721e_evm/J721E_pinmux.h>
#include <ti/board/src/j721e_evm/include/board_pinmux.h>
#include <ti/board/src/j721e_evm/include/board_cfg.h>
#include <ti/osal/HwiP.h>
#ifdef CPU_mcu1_0
#include <ti/csl/soc/j721e/src/cslr_intr_mcu_r5fss0_core0.h>
#endif
#include <ti/osal/RegisterIntr.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/tisci_protocol.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_core.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_irq.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_shared.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_ra.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_udmap.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_psil.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/rm/tisci_rm_proxy.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/drv/sciclient/include/sciclient_rm.h>
#include <utils/console_io/include/app_log.h>
/** \brief ePWM instance IDs */
#define APP_EPWM0_INST_ID ( 0 )
#define APP_EPWM1_INST_ID ( 1 )
#define APP_EPWM2_INST_ID ( 2 )
#define APP_EPWM3_INST_ID ( 3 )
#define APP_EPWM4_INST_ID ( 4 )
#define APP_EPWM5_INST_ID ( 5 )
/** \brief Kick0 protection register unlock value. */
#define KICK0_UNLOCK_VAL ( 0x68EF3490 )
/** \brief Kick1 protection register unlock value. */
#define KICK1_UNLOCK_VAL ( 0xD172BC5A )
/** \brief Enable clocks to epwm. */
#define APP_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL_TB_CLKEN_EN ( 0x1U )
#define CSL_EPWM_HR_DELAY_BUS_SEL_CMPAHR (PWMSS_EPWM_HRCTL_DELBUSSEL_SEL_CMPAHR)
/**< Select CMPAHR(8) bus from compare module of EPWM (default on reset). */
#define CSL_EPWM_HR_DELAY_BUS_SEL_TBPHSHR (PWMSS_EPWM_HRCTL_DELBUSSEL_SEL_TBPHSHR)
/**< Select TBPHSHR(8) bus from time base module. */
/* Configure EPWM pads */
static Board_STATUS EpwmAppCfgEPwmPads(void);
/* Enable ePWM clock */
static Board_STATUS EpwmAppTbClockEnable(uint32_t pwmId);
static Board_STATUS Board_moduleClockInit(void);
#ifdef CPU_mcu1_0
static int32_t configureIntrRouter(void);
static int32_t registerePWMInt(uint32_t baseAddr);
#endif
/* ========================================================================== */
/* Macros */
/* ========================================================================== */
/*
* Configurable parameters
*/
/**
* \brief PWM instance base address.
*
* Note: If changed to other instance, PRCM and pinmux changes needs to be
* taken care in the application.
*/
#define APP_EHRPWM_INST_BASE_ADDR (CSL_EHRPWM0_EPWM_BASE)
#ifdef CPU_mcu1_0
/* MAIN2MCU_PLS_INTRTR0 output interrupt */
#define MAIN2MCU_PLS_INTR0_OUT ( 0 )
/* VIM input interrupt */
#define MCU0_INTR_IN_EPWM0_INT ( CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_PLS_INTRTR0_OUTP_0 + MAIN2MCU_PLS_INTR0_OUT )
#endif
/**
* \brief Output channel - A or B.
*
* Note: If changed to channel B, pinmux changes needs to be taken care
* in the application.
*/
#define APP_EHRPWM_OUTPUT_CH (CSL_EPWM_OUTPUT_CH_A)
/** \brief Frequency of PWM output signal in Hz - 1 KHz is selected */
#define APP_EHRPWM_OUT_FREQ (64*100U)
/** \brief Duty Cycle of PWM output signal in % - give value from 0 to 100 */
#define APP_EHRPWM_DUTY_CYCLE (25U)
/**
* \brief Functional clock to the PWMSS.
* Fixed for the platform - can't be changed.
*/
#define SOC_EHRPWM_MODULE_FREQ (133U * 1000U * 1000U)
/** \brief TB frequency in Hz - so that /4 divider is used */
#define APP_EHRPWM_TB_FREQ (SOC_EHRPWM_MODULE_FREQ / 4U)
/**
* \brief PRD value - this determines the period
*
* PRD = (TBCLK/PWM FREQ) / 2
* NOTE: /2 is added becasue up&down counter is selected. So period is 2 times
*/
#define APP_EHRPWM_PRD_VAL ((APP_EHRPWM_TB_FREQ \
/ APP_EHRPWM_OUT_FREQ) / 2U)
/**
* \brief COMPA value - this determines the duty cycle
*
* COMPA = (PRD - ((dutycycle * PRD) / 100)
*/
#define APP_EHRPWM_COMPA_VAL (APP_EHRPWM_PRD_VAL - \
((APP_EHRPWM_DUTY_CYCLE * \
APP_EHRPWM_PRD_VAL) / 100U))
/** \brief Structure holding the EPWM configuration parameters. */
typedef struct CSL_EpwmAppPwmCfg
{
CSL_EpwmTimebaseCfg_t tbCfg;
/**< Timebase Sub-module configuration data structure. */
CSL_EpwmCounterCmpCfg_t ccCfg;
/**< Counter comparator values . */
CSL_EpwmAqActionCfg_t aqCfg;
/**< Action Qualifier Sub-module configuration data structure. */
CSL_EpwmDeadbandCfg_t dbCfg;
/**< Dead band Sub-module configuration data structure. */
CSL_EpwmChopperCfg_t chpCfg;
/**< Chopper sub-module configuration data structure. */
CSL_EpwmTripzoneCfg_t tzCfg;
/**< Trip-zone sub-module configuration data structure. */
CSL_EpwmEtCfg_t etCfg;
/**< Event Trigger sub-module configuration data structure. */
CSL_EpwmHighResolutionCfg_t hrCfg;
/**< High Resolution sub-module configuration data structure. */
} CSL_EpwmAppPwmCfg_t;
typedef struct CSL_EpwmAppPwmObj
{
uint32_t pwmCh;
/**< EPWM channel [A or B]. */
uint32_t instAddr;
/**< EPWM instance address. */
uint32_t funcClk;
/**< Functional clock(in Hz) input to the PWMSS. */
uint32_t enableDeadband;
/**< Enable dead band sub-module processing. */
uint32_t enableChopper;
/**< Enable chopper sub-module processing. */
uint32_t enableTripZone;
/**< Enable Trip zone processing. */
uint32_t enableEventTrigger;
/**< Enable Event trigger. */
uint32_t enableHighResolution;
/**< Enable High resolution pwm feature. */
CSL_EpwmAppPwmCfg_t pwmCfg;
/**< EPWM configuration data structure. */
} CSL_EpwmAppPwmObj_t;
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/** \brief IP default configuration */
static CSL_EpwmAppPwmObj_t gAppPwmObj =
{
APP_EHRPWM_OUTPUT_CH, /* pwmCh */
APP_EHRPWM_INST_BASE_ADDR, /* instAddr */
SOC_EHRPWM_MODULE_FREQ, /* funcClk */
FALSE, /* enableDeadband */
FALSE, /* enableChopper */
FALSE, /* enableTripzone */
#ifdef CPU_mcu1_0
TRUE, /* enableEventTrigger */
#else
FALSE, /* enableEventTrigger */
#endif
FALSE, /* enableHighResolution */
/* CSL_EpwmAppPwmCfg_t*/
{
/* CSL_EpwmTimebaseCfg_t */
{
APP_EHRPWM_TB_FREQ, /* tbClk */
APP_EHRPWM_OUT_FREQ, /* pwmtbCounterFreqPrd */
CSL_EPWM_TB_COUNTER_DIR_UP, /* tbCntrDirection */
FALSE, /* enableSynchronization */
PWMSS_EPWM_TBCTL_PHSDIR_COUNT_DOWN, /* cntDirAfterSync */
0U, /* phsCountAfterSync */
PWMSS_EPWM_TBCTL_SYNCOSEL_EPWMXSYNC /* syncOutSrc */
},
/* CSL_EpwmCounterCmpCfg_t */
{
APP_EHRPWM_COMPA_VAL, /* cmpAValue */
APP_EHRPWM_COMPA_VAL /* cmpBValue */
},
/* CSL_EpwmAqActionCfg_t */
{
CSL_EPWM_AQ_ACTION_DONOTHING, /* zeroAction */
CSL_EPWM_AQ_ACTION_LOW, /* prdAction */
CSL_EPWM_AQ_ACTION_HIGH, /* cmpAUpAction */
CSL_EPWM_AQ_ACTION_DONOTHING, /* cmpADownAction */
CSL_EPWM_AQ_ACTION_DONOTHING, /* cmpBUpAction */
CSL_EPWM_AQ_ACTION_DONOTHING /* cmpBDownAction */
},
/* CSL_EpwmDeadbandCfg_t */
{
CSL_EPWM_DB_IN_MODE_A_RED_A_FED, /* inputMode */
CSL_EPWM_DB_OUT_MODE_BYPASS, /* outputMode */
CSL_EPWM_DB_POL_SEL_ACTV_HIGH, /* polaritySelect */
0U, /* risingEdgeDelay */
0U /* fallingEdgeDelay */
},
/* CSL_EpwmChopperCfg_t */
{
CSL_EPWM_CHP_DUTY_CYCLE_PERC_12PNT5, /* dutyCycle */
CSL_EPWM_CHP_CLK_FREQ_DIV_BY_1, /* clkFrequency */
CSL_EPWM_CHP_OSHT_WIDTH_1XSYSOUT_BY_8 /* oneShotPulseWidth */
},
/* CSL_EpwmTripzoneCfg_t */
{
CSL_EPWM_TZ_TRIP_ACTION_DO_NOTHING, /* tripAction */
CSL_EPWM_TZ_EVENT_ONE_SHOT, /* tripEvtType */
0U, /* tripPin */
FALSE /* enableTripIntr */
},
/* CSL_EpwmEtCfg_t */
{
CSL_EPWM_ET_INTR_EVT_CNT_EQ_PRD, /* intrEvtSource */
CSL_EPWM_ET_INTR_PERIOD_FIRST_EVT /* intrPrd */
}
}
};
static pinmuxPerCfg_t gEHRPWMIOPinCfg[] =
{
/* EHRPWM0_A -> V29 */
{
PIN_RGMII5_TD2, PIN_MODE(6) | \
((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
},
{PINMUX_END}
};
static pinmuxModuleCfg_t gEHRPWMPinCfg[] =
{
{0, TRUE, gEHRPWMIOPinCfg},
{PINMUX_END}
};
static pinmuxBoardCfg_t gBasicDemoPinmuxDataInfo[] =
{
{0, gEHRPWMPinCfg},
{PINMUX_END}
};
static uint32_t gBoardClkModuleMainID[] = {
TISCI_DEV_EHRPWM0,
};
#ifdef CPU_mcu1_0
static volatile uint32_t gNumIsr = 0U;
static HwiP_Handle gHwiPHandle;
#endif
/* ========================================================================== */
/* Internal Function Declarations */
/* ========================================================================== */
static void CSL_epwmAppPwmCfg(CSL_EpwmAppPwmObj_t *pObj);
static Board_STATUS EPwmAppGetPwmFuncClock(CSL_EpwmAppPwmObj_t *pObj);
static void EpwmAppTimebaseModuleCfg(uint32_t baseAddr,
uint32_t pwmFuncClk,
CSL_EpwmTimebaseCfg_t *pTbCfg);
static void EpwmAppCounterComparatorCfg(uint32_t baseAddr,
CSL_EpwmCounterCmpCfg_t *pCcCfg);
static Board_STATUS padConfig_prcmEnable(void);
void test_csl_epwm_duty_cycle_test_app (void);
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
static void StartupEmulatorWaitPFxn (void)
{
volatile uint32_t enableDebug = 1;
do
{
}while (enableDebug);
}
void test_csl_epwm_duty_cycle_test_app (void)
{
CSL_EpwmAppPwmObj_t *pObj = &gAppPwmObj;
Board_STATUS status;
StartupEmulatorWaitPFxn();
/* Do PRCM enable and pad config for PWM */
status = padConfig_prcmEnable();
if (status == BOARD_SOK)
{
/* Get ePWM module functional clock */
status = EPwmAppGetPwmFuncClock(pObj);
}
if (status == BOARD_SOK)
{
/* EPWM channel configuration */
CSL_epwmAppPwmCfg(pObj);
}
/* for test purpose only */
while(1)
{
appLogWaitMsecs(100u);
}
}
/**
* \brief This API configures the ePWM module
*
* \param pObj pointer to the ePwm object data structure.
*/
static void CSL_epwmAppPwmCfg(CSL_EpwmAppPwmObj_t *pObj)
{
uint32_t baseAddr = pObj->instAddr;
uint32_t pwmCh = pObj->pwmCh;
uint32_t pwmFuncClk = pObj->funcClk;
CSL_EpwmAppPwmCfg_t *pPwmCfg = &pObj->pwmCfg;
/* Configure the Time base Sub-Module */
EpwmAppTimebaseModuleCfg(baseAddr, pwmFuncClk, &pPwmCfg->tbCfg);
/* Counter-Comparator Sub-Module Configuration */
EpwmAppCounterComparatorCfg(baseAddr, &pPwmCfg->ccCfg);
/* Configure Action Qualifier */
CSL_epwmAqActionOnOutputCfg(baseAddr, pwmCh, &pPwmCfg->aqCfg);
/* Dead band sub-module configuration */
if (TRUE == pObj->enableDeadband)
{
/* Enable and configure dead band sub module */
CSL_epwmDeadbandCfg(baseAddr, &pPwmCfg->dbCfg);
}
else
{
/* Bypass dead band sub module */
CSL_epwmDeadbandBypass(baseAddr);
}
/* Chopper sub-module configuration */
if (TRUE == pObj->enableChopper)
{
/* Configure chopper sub - module */
CSL_epwmChopperCfg(baseAddr, &pPwmCfg->chpCfg);
/* Enable Chopper */
CSL_epwmChopperEnable(baseAddr, TRUE);
}
else
{
/* Disable Chopper */
CSL_epwmChopperEnable(baseAddr, FALSE);
}
/* Trip Zone Sub-Module Configuration */
if (TRUE == pObj->enableTripZone)
{
/* Configure the Trip action */
CSL_epwmTzTriggerTripAction(
baseAddr, CSL_EPWM_TZ_TRIP_ACTION_HIGH, pwmCh);
/* Enable the Trip event */
CSL_epwmTzTripEventEnable(
baseAddr, pPwmCfg->tzCfg.tripEvtType, pPwmCfg->tzCfg.tripPin);
}
else
{
/* Disable trip zone event handling and ignore all trip zone events */
CSL_epwmTzTripEventDisable(
baseAddr, CSL_EPWM_TZ_EVENT_ONE_SHOT, pPwmCfg->tzCfg.tripPin);
CSL_epwmTzTripEventDisable(
baseAddr, CSL_EPWM_TZ_EVENT_CYCLE_BY_CYCLE, pPwmCfg->tzCfg.tripPin);
}
/* Event trigger sub - module configuration */
if (TRUE == pObj->enableEventTrigger)
{
/* Configure the Event trigger processing */
CSL_epwmEtIntrCfg(
baseAddr, pPwmCfg->etCfg.intrEvtSource, pPwmCfg->etCfg.intrPrd);
CSL_epwmEtIntrEnable(baseAddr);
}
else
{
/* Disable Event trigger interrupts */
CSL_epwmEtIntrDisable(baseAddr);
}
/**
* High resolution feature is supported only on PWM A channel. If channel
* is A then proceed with High Resolution processing.
*/
if (CSL_EPWM_OUTPUT_CH_A == pwmCh)
{
/**
* High resolution feature is not supported in AM64x SOC
*/
if (TRUE == pObj->enableHighResolution)
{
/* configure high resolution feature */
CSL_epwmHighResolutionCfg(
baseAddr,
pPwmCfg->hrCfg.delayBusSelect,
pPwmCfg->hrCfg.delayMode);
if (CSL_EPWM_HR_DELAY_BUS_SEL_CMPAHR ==
pPwmCfg->hrCfg.delayBusSelect)
{
/* Load comparator A High-resolution counter value */
CSL_epwmHrLoadCmpAHrValue(
baseAddr,
pPwmCfg->hrCfg.cmpAHighResVal,
CSL_EPWM_HR_REG_ACT_LOAD_CNT_ZRO_PULSE);
}
else /* CSL_EPWM_HR_DELAY_BUS_SEL_TBPHSHR */
{
/* Load Timebase phase high resolution value */
CSL_epwmHrLoadTbPhaseHrValue(
baseAddr, pPwmCfg->hrCfg.tbPhaseHighResVal);
}
}
else
{
/* Disable High Resolution Feature */
CSL_epwmHighResolutionDisable(baseAddr);
}
}
return;
}
/**
* \brief This API configures the Timebase Sub-module.
*
* \param baseAddr Base address of PWMSS instance used
* \param pwmFuncClk PWM functional clock value in Hz
* \param pTbCfg Pointer to the Time base sub-module configuration
* data structure
*/
static void EpwmAppTimebaseModuleCfg(uint32_t baseAddr,
uint32_t pwmFuncClk,
CSL_EpwmTimebaseCfg_t *pTbCfg)
{
/* Configure Time base clock */
CSL_epwmTbTimebaseClkCfg(baseAddr, pTbCfg->tbClk, pwmFuncClk);
/* Configure PWM time base counter frequency and direction */
CSL_epwmTbPwmFreqCfg(
baseAddr,
pTbCfg->tbClk,
pTbCfg->pwmtbCounterFreqPrd,
pTbCfg->tbCntrDirection,
CSL_EPWM_SHADOW_REG_CTRL_ENABLE);
if (TRUE == pTbCfg->enableSynchronization)
{
/* Enable Synchronization */
CSL_epwmTbSyncEnable(
baseAddr, pTbCfg->phsCountAfterSync, pTbCfg->cntDirAfterSync);
}
else
{
/* Disable Synchronization */
CSL_epwmTbSyncDisable(baseAddr);
}
/* Configure Sync out signal */
CSL_epwmTbSetSyncOutMode(baseAddr, pTbCfg->syncOutSrc);
/* Configure the emulation behaviour */
CSL_epwmTbSetEmulationMode(baseAddr, EPWM_TB_EMU_MODE_FREE_RUN);
return;
}
/**
* \brief This API configures the Counter-Comparator Sub-module.
*
* \param baseAddr Base address of PWMSS instance used
* \param pCcCfg Pointer to the Counter-Comparator Sub-module
* configuration data structure
*/
static void EpwmAppCounterComparatorCfg(uint32_t baseAddr,
CSL_EpwmCounterCmpCfg_t *pCcCfg)
{
/* Counter Comparator A configuration */
CSL_epwmCounterComparatorCfg(
baseAddr,
CSL_EPWM_CC_CMP_A,
pCcCfg->cmpAValue,
CSL_EPWM_SHADOW_REG_CTRL_ENABLE,
CSL_EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO,
TRUE);
/* Counter Comparator B configuration */
CSL_epwmCounterComparatorCfg(
baseAddr,
CSL_EPWM_CC_CMP_B,
pCcCfg->cmpBValue,
CSL_EPWM_SHADOW_REG_CTRL_ENABLE,
CSL_EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO,
TRUE);
return;
}
static Board_STATUS padConfig_prcmEnable(void)
{
Board_STATUS status;
/* Configure ePWM pads */
status = EpwmAppCfgEPwmPads();
if (status == BOARD_SOK)
{
/* Enable ePWM module */
status = Board_moduleClockInit();
}
if (status == BOARD_SOK)
{
/* Enable EPWM module time base clock */
status = EpwmAppTbClockEnable(APP_EPWM0_INST_ID);
}
#ifdef CPU_mcu1_0
if (status == BOARD_SOK)
{
/* Configure interrupt router */
status = configureIntrRouter();
}
if (status == BOARD_SOK)
{
registerePWMInt(APP_EHRPWM_INST_BASE_ADDR);
}
#endif
return status;
}
/* Configure EPWM pads */
static Board_STATUS EpwmAppCfgEPwmPads(void)
{
return Board_pinmuxUpdate(gBasicDemoPinmuxDataInfo,
BOARD_SOC_DOMAIN_MAIN);
}
/* Enable ePWM time base clock */
static Board_STATUS EpwmAppTbClockEnable(uint32_t pwmId)
{
int32_t regVal;
Board_STATUS status = BOARD_SOK;
CSL_main_ctrl_mmr_cfg0Regs *pMainCtrlMmrCfg0Regs;
volatile uint32_t *pMainCtrlMmrCfg0Reg;
pMainCtrlMmrCfg0Regs = (CSL_main_ctrl_mmr_cfg0Regs *)CSL_CTRL_MMR0_CFG0_BASE;
pMainCtrlMmrCfg0Reg = &pMainCtrlMmrCfg0Regs->LOCK1_KICK0;
regVal = HW_RD_REG32(pMainCtrlMmrCfg0Reg);
if (!(regVal & 0x1))
{
/* Unlock CTLR_MMR0 registers */
pMainCtrlMmrCfg0Reg = &pMainCtrlMmrCfg0Regs->LOCK1_KICK0;
HW_WR_REG32(pMainCtrlMmrCfg0Reg, KICK0_UNLOCK_VAL);
pMainCtrlMmrCfg0Reg = &pMainCtrlMmrCfg0Regs->LOCK1_KICK1;
HW_WR_REG32(pMainCtrlMmrCfg0Reg, KICK1_UNLOCK_VAL);
pMainCtrlMmrCfg0Reg = &pMainCtrlMmrCfg0Regs->LOCK1_KICK0;
do {
regVal = HW_RD_REG32(pMainCtrlMmrCfg0Reg);
} while (!(regVal & 0x1));
}
pMainCtrlMmrCfg0Reg = &pMainCtrlMmrCfg0Regs->EPWM0_CTRL + pwmId;
HW_WR_FIELD32(pMainCtrlMmrCfg0Reg,
CSL_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL_TB_CLKEN,
APP_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL_TB_CLKEN_EN);
return status;
}
/* Get ePWM module functional clock */
static Board_STATUS EPwmAppGetPwmFuncClock(CSL_EpwmAppPwmObj_t *pObj)
{
uint64_t respClkRate;
uint32_t prdVal;
int32_t nRet;
Board_STATUS status = BOARD_SOK;
/* Get ePWM0 module clock frequency */
nRet = Sciclient_pmGetModuleClkFreq(TISCI_DEV_EHRPWM0,
TISCI_DEV_EHRPWM0_VBUSP_CLK,
&respClkRate,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (nRet != CSL_PASS)
{
status = BOARD_FAIL;
}
if (status == BOARD_SOK)
{
/* Update object based on ePWM module frequency */
pObj->funcClk = (uint32_t)respClkRate;
pObj->pwmCfg.tbCfg.tbClk = pObj->funcClk / 4;
prdVal = (pObj->pwmCfg.tbCfg.tbClk / pObj->pwmCfg.tbCfg.pwmtbCounterFreqPrd) / 2;
pObj->pwmCfg.ccCfg.cmpAValue = prdVal - ((APP_EHRPWM_DUTY_CYCLE * prdVal)/ 100U);
pObj->pwmCfg.ccCfg.cmpBValue = pObj->pwmCfg.ccCfg.cmpAValue;
}
return status;
}
#ifdef CPU_mcu1_0
static int32_t configureIntrRouter(void)
{
struct tisci_msg_rm_irq_set_req rmIrqReq;
struct tisci_msg_rm_irq_set_resp rmIrqResp;
int32_t status;
memset (&rmIrqReq,0,sizeof(rmIrqReq));
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
rmIrqReq.src_id = TISCI_DEV_EHRPWM0;
rmIrqReq.src_index = 0;
/* Set the destination interrupt */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
rmIrqReq.dst_id = TISCI_DEV_MCU_R5FSS0_CORE0;
rmIrqReq.dst_host_irq = MCU0_INTR_IN_EPWM0_INT;
status = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != 0)
{
appLogPrintf("Sciclient_rmIrqSet err: %d !!!\n", status);
}
return status;
}
#endif
extern Board_STATUS Board_moduleClockEnable(uint32_t moduleId);
static Board_STATUS Board_moduleClockInit(void)
{
Board_STATUS status = BOARD_SOK;
uint32_t index;
uint32_t loopCount;
loopCount = sizeof(gBoardClkModuleMainID) / sizeof(uint32_t);
for(index = 0; index < loopCount; index++)
{
status = Board_moduleClockEnable(gBoardClkModuleMainID[index]);
if(status != BOARD_SOK)
{
return BOARD_INIT_CLOCK_FAIL;
}
}
return status;
}
#ifdef CPU_mcu1_0
static void AppPwmIntrISR(uintptr_t arg)
{
volatile uint16_t status = CSL_epwmEtIntrStatus(APP_EHRPWM_INST_BASE_ADDR);
status = status;
CSL_epwmEtIntrClear(APP_EHRPWM_INST_BASE_ADDR);
gNumIsr++;
return;
}
static int32_t registerePWMInt(uint32_t baseAddr)
{
int32_t testStatus;
OsalInterruptRetCode_e retVal;
OsalRegisterIntrParams_t interruptRegParams;
/* Initialize with defaults */
Osal_RegisterInterrupt_initParams(&interruptRegParams);
/* Populate the interrupt parameters */
interruptRegParams.corepacConfig.arg=(uintptr_t) baseAddr;
interruptRegParams.corepacConfig.name=NULL;
interruptRegParams.corepacConfig.isrRoutine=AppPwmIntrISR;
interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE;
interruptRegParams.corepacConfig.priority = 0x20U;
interruptRegParams.corepacConfig.intVecNum=MCU0_INTR_IN_EPWM0_INT; /* Host Interrupt vector */
interruptRegParams.corepacConfig.corepacEventNum = 0u;
/* Register interrupts */
retVal = Osal_RegisterInterrupt(&interruptRegParams,&(gHwiPHandle));
if (retVal == OSAL_INT_SUCCESS)
{
testStatus = 0;
}
else
{
testStatus = -1;
}
return (testStatus);
}
#endif
#endif
Thanks.