• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 98 subscribers
  • Views 921 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VMXEVM: PCIe EP mode testing with second TDA4VM in RC mode

Gunter Schmer
Genius 14412 points

Part Number: TDA4VMXEVM

Hi,

there is some really good documentation for the J7ES EVM PCIe EP mode test with a second J7 EVM in RC mode.

http://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_End_Point.html

A customer is is trying to configure the J7 PCIe EP mode correctly based on these instructions and then is using the second J7 EVM in PCIe RC mode. However after powering up the J7 EP, and subsequently the J7 RC, the EP does not seem to be enumerated.

Here are the logs:

EP side:

root@j7-evm-ep:/sys/kernel/config/pci_ep# lspci
00:00.0 Class 0604: 104c:b00d
00:00.0 Class 0604: 104c:b00d
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci
pci-epf-ntb/ pci_epf_test/
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/
baseclass_code deviceid msi_interrupts progif_code subclass_code subsys_vendor_id
cache_line_size interrupt_pin msix_interrupts revid subsys_id vendorid
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/vendorid
0x104c
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/deviceid
0xb00d
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/msi_interrupts
2
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/msix_interrupts
2
root@j7-evm-ep:/sys/kernel/config/pci_ep# ls -l controllers/2900000.pcie-ep/
total 0
lrwxrwxrwx 1 root root 0 Sep 20 23:48 func1 -> ../../../pci_ep/functions/pci_epf_test/func1
-rw-r--r-- 1 root root 65536 Sep 20 23:49 start
root@j7-evm-ep:/sys/kernel/config/pci_ep# cat controllers/2900000.pcie-ep/start
1

RC side:

root@j7-evm-rc:~# ls /sys/kernel/config/pci_ep/controllers/
root@j7-evm-rc:~#
root@j7-evm-rc:~# lspci
00:00.0 Class 0604: 104c:b00d
00:00.0 Class 0604: 104c:b00d
00:00.0 Class 0604: 104c:b00d
root@j7-evm-rc:~# ls /dev/pc*
ls: /dev/pc*: No such file or directory

Could you review this and let me know where to look here? Could you confirm the Switch settings for both J7 RC and J7 EP EVMs?

We will double-check everything.

Thanks!

--Gunter

  • 0
    TI__Genius 14412 points

    Hi,

    one follow-up comment about the documentation

    It speaks about an "Alpha" vs "Beta" EVM. 

    How exactly do we distinguish between Alpha vs Beta, and specifically the selection of the dts files/filenames?

    Thanks,

    --Gunter

  • 0 in reply to Gunter Schmer
    TI__Genius 14412 points

    Hi,

    to confirm, these are the switch settings currently used by the customer

    SW3 dip switch:

    For RC, 1, 3, 4 are OFF. The others are ON.

    For EP, 1, 3, 4, 5, 6 are OFF. The others are ON.

    Regards,

    --Gunter

  • 0 in reply to Gunter Schmer
    TI__Genius 14412 points

    Hi,

    could we have an update?

    Since this test involves J7 as RC and J7 as EP, we are attaching both dmesg for RC and EP, as well as dts files from /sys/firmware/device-tree/base on running J7s, to check that everything is enabled. We are fairly certain that the DTB is getting updated appropriately as the pcie-ep@29200000 is enabled for the J7 in EP mode.

    Regards,

    --Gunter

    PCIe.zip

  • 0 in reply to Gunter Schmer
    TI__Genius 14412 points

    Hi,

    testing the J7 EVM PCIe RC mode, I determined that the working SW3 setting is

    RC Mode SW3: 1,3,4,5,6 are OFF, the rest ON.

    Regards,

    --Gunter

  • 0 in reply to Gunter Schmer
    TI__Genius 14412 points

    Hi,

    since there are two J7 EVMs in play for this test, we have checked each J7 EVM individually, and apparently one of the J7 EVMs does not work properly, there may be a board level issue.

    The working EVM can be configured into RC mode and can enumerate PCIe cards. The working EVM can also be configured into EP mode and connect to a non-J7 Host, which can enumerate the J7 EP.

     The failing J7 EVM (same switch setting, no other difference) somehow cannot operate in either RC mode or EP mode, there may be a board level problem.

    Regards,

    --Gunter

  • 0 in reply to Gunter Schmer
    TI__Mastermind 23125 points

    Gunter, 

    What is the symptom of the failing EVM?

    once the EVM is checked out, one note my colleague pointed out was regarding to the to the reset pin, where most straightforward methods is to remove the resistor on the cable so reset does not propogate from RC to EP on board-2-board configuration. Please also confirm you started EP first then RC. 

    As the EVM revisions, they are related to the SOC power solution. Alpha revision used TPS65917 (thus the file names), while Beta used TPS65941. You should see a E7 revision code on the SOM (the board with J7 on it) module of your EVM, then you have a beta. 

    regards

    jian