PROCESSOR-SDK-AM65X: Latest EMIF file

Sepeedah Zadeh

Hello team,

My customer is needing to confirm the correct AM65x EMIF file to work with SDK 7.0. The latest we’ve found is version 2.02, can you confirm please?

Thanks!

over 5 years ago

0 Karthik Ramanan over 5 years ago

TI__Guru** 113810 points

Hi,

Yes. The latest version is always found here and it is 2.02 as on today.

https://www.ti.com/tool/SITARA-DDR-CONFIG-TOOL

Regards

Karthik

0 Sepeedah Zadeh over 5 years ago in reply to Karthik Ramanan

TI__Expert 3140 points

Thanks Karthik!

0 Andrea Wang over 5 years ago in reply to Karthik Ramanan

Intellectual 380 points

Hi Karthik,

Thanks for the confirmation. Can you explain what some in the EMIF changes were for? We're seeing some differences in the 1.98 and 2.02 generated values but don't understand why they are different. Is there a difference with how silicon 2.0 initializes and trains the DDR4?

Thanks,

Andrea

0 Kevin S over 5 years ago in reply to Andrea Wang

TI__Mastermind 38540 points

Hi,

We are checking internally.

Thanks,
Kevin

0 Andrea Wang over 5 years ago in reply to Kevin S

Intellectual 380 points

Hi Kevin,

Any additional info on this? We had to mix and match 1.98 and 2.02 to get our custom board to boot on silicon 2 while 1.98 worked fine on silicon 1... no changes with how we connected DDR between the two versions. Same DDR chips as well.

Thanks,

Andrea

0 Kevin S over 4 years ago in reply to Andrea Wang

TI__Mastermind 38540 points

Hi Andrea,

I do not have any additional information at this time. While I wait to hear back internally, can you comment on the differences and changes you have had to make to get your custom board to work with silicon 2.0?

Thanks,
Kevin

0 Andrea Wang over 4 years ago in reply to Kevin S

Intellectual 380 points

Hi Kevin,

The ones that made the largest difference was changing the slew rate back to the slower mode

#define DDRPHY_ACIOCR0 0x30070000

and changing the last DDRPHY settings back to 1.98 settings (2.02 set these 3 to 0x01264300)

#define DDRPHY_DX8SL0DQSCTL 0x01264000
#define DDRPHY_DX8SL1DQSCTL 0x01264000
#define DDRPHY_DX8SL2DQSCTL 0x01264000

Thanks,

Andrea

0 Andrea Wang over 4 years ago in reply to Andrea Wang

Intellectual 380 points

Hi Kevin,

Any updates?

Thanks,

Andrea

0 Kevin S over 4 years ago in reply to Andrea Wang

TI__Mastermind 38540 points

Hi Andrea,

My understanding from the design team is that the only change between 1.0 vs 2.0 was to separate out ZQ control between cmd/addr and data lanes, but this should not impact logical / state machine aspect of the DDR4 initialization and training.

I have not received any feedback on differences between the two versions of the XLS tool. However, optimal IO settings may vary from PCB to PCB, which is why slew rate is configurable in the XLS tool. Based on your description, it appears a slower slew rate may work better for your system.

Best regards,
Kevin

0 Andrea Wang over 4 years ago in reply to Kevin S

Intellectual 380 points

Good to know. Thanks for looking into this.

Best,

Andrea

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PROCESSOR-SDK-AM65X: Latest EMIF file