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Original question:

TMS320C6678: TSIP Clocks while power up sequence.

TMS320C6678: TSIP Clocks while power up sequence.

erez cohen
Intellectual 595 points
Part Number: TMS320C6678

Tom,

Next to your replay TSIP clocks should be applied after stabilization of 1.8V and before Reset is released, please advise which Reset we are talking about Reset, Resetfull or POR?

Note: my design supports IO before core power up sequence and currently TSIP clocks supplied after Reset released and prior driving POR signal. is that OKay? 

Erez.

  • 0
    TI__Mastermind 46460 points

    Erez,

    Once power is stable, RESETFULLz and PORz are equivalent.  They both provide a full hardware reset.  RESETz is the warm reset that has reduced reset control and it normally used after device boot for limited reset that is managed under software control.

    At initial start-up, we recommend that RESETz be ramped up early - perhaps as soon 1.8V supply ramps.  That leaves RESETFULLz and PORz to release the device from reset and to latch the boot mode pins.  The last of these 2 to rise will allow the device to boot.

    As long as the TSIP clock is enabled after the 1.8V supply is stable and before the later of PORz or RESETFULLz rising, then you have met the requirement.

    Tom