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CCS: linux boot fail if start from pdk MLO througth Uboot

dario iannaccio
Intellectual 870 points

Tool/software: Code Composer Studio

Hi experts,

   we have a (another) little problem, now is about the SMP, our SOC architecture is K2H14.

To perform boot of DSPs and ARMs (together) our client want to use MLO (contents in TI PDK).
The used PDK is contents in ti-processor-sdk-rtos-k2hk-evm-05.02.00.10-Linux-x86-Install.bin

I have found a little problem with out2rprc.exe, then I have used an opensource tool elf2rprc
with some correction to able to start ARM and DSP application.

I have configured for our custom board a uboot u-boot-2019.01 (packet content into
ti-processor-sdk-linux-k2hk-evm-06.01.00.08-Linux-x86-Install.bin).

Now, if I configure u-boot with its SPL linux run on all ARM core in SMP mode (as client request).

As you can see here:

U-Boot SPL 2019.01-svn10 (Sep 22 2020 - 20:32:37 +0200)
Trying to boot from SPI


U-Boot 2019.01-svn10 (Sep 22 2020 - 20:32:37 +0200)

CPU: 66AK2Hx SR3.1 (XXX)
Model: XXXXXXXX XXXX board (UBoot)
DRAM:  DDR3A memory bank [XXXX-K2H-2G1600SED]
DDR3 speed 1600
DRAM: 2 GiB (includes reported below)
2 GiB
***************************************************************
Relocation Offset is: f3f46000
Relocating to fff46000, new gd at fdf05ed8, sp at fdf05eb0
***************************************************************
usb dr_mode not found
NAND:  
Device found, Manufacturer ID: 0x2c, Chip ID: 0xb3
Micron MT29F8G16ADBDAH4
1024 MiB
Loading Environment from SPI Flash... spi_flash_std_probe: slave=fdf0bb98, cs=0
SF: Detected mt25qu256a with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
turn_off_all_dsps#34: Called disabling DSP
Net:   eth0: netcp@2000000, eth1: netcp@slave-1, eth2: netcp@slave-2, eth3: netcp@slave-3

Net IF Nr: 4
Hit any key to stop autoboot: 1 0
=> run ubiUpgrade

netcp@2000000 Waiting for SGMII auto negotiation to complete. done
Using netcp@2000000 device
TFTP from server 192.168.111.150; our IP address is 192.168.111.11
Filename '/tftpboot/XXXXX_RootFS.ubi'.
Load address: 0x80000000
Loading: #################################################################
         #################################################################
  .....
         #################################################################
         #################################################################
         ####
         4.5 MiB/s
done
Bytes transferred = 132513792 (7e60000 hex)

NAND erase.part: device 0 offset 0x0, size 0xc800000
Erasing at 0xc7e0000 -- 100% complete.
OK

NAND write: device 0 offset 0x0, size 0x7e60000
 132513792 bytes written: OK

=> run bootcmd1 bootcmd2 bootcmd3 bootcmd4
ubi0: attaching mtd1
ubi0: scanning is finished
ubi0: volume 0 ("rootfs") re-sized from 1009 to 1436 LEBs
ubi0: attached mtd1 (name "ubifs2", size 200 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 1600, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 1/0, WL threshold: 4096, image sequence number: 260444989
ubi0: available PEBs: 0, total reserved PEBs: 1600, PEBs reserved for bad PEB handling: 160
<DIR>        7392  Mon Apr 06 14:50:46 2020  bin
<DIR>         160  Mon Apr 06 14:50:46 2020  dev
<DIR>        6648  Tue May 05 16:12:48 2020  etc
<DIR>        7296  Tue May 19 16:59:35 2020  lib
<DIR>         232  Mon Apr 06 14:50:46 2020  mnt
<DIR>         224  Mon Apr 06 14:50:46 2020  opt
<DIR>         160  Mon Apr 06 14:50:47 2020  run
<DIR>         224  Mon Apr 06 14:50:47 2020  srv
<DIR>         160  Mon Apr 06 14:50:47 2020  tmp
<DIR>         160  Mon Apr 06 14:50:47 2020  sys
<DIR>         808  Mon Apr 06 14:50:49 2020  var
<DIR>         752  Mon Apr 06 14:50:48 2020  usr
<DIR>         488  Tue Sep 22 19:35:06 2020  boot
<DIR>         224  Mon Jun 01 13:01:10 2020  home
<LNK>          20  Mon Apr 06 14:50:49 2020  init
<DIR>         160  Mon Apr 06 14:50:47 2020  proc
<DIR>        7744  Mon Apr 06 14:50:47 2020  sbin
<DIR>         160  Mon Apr 06 14:50:46 2020  media

netcp@2000000 Waiting for SGMII auto negotiation to complete. done
Using netcp@2000000 device
TFTP from server 192.168.111.150; our IP address is 192.168.111.11
Filename '/tftpboot/XXXXX_multi.itb'.
Load address: 0x90000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         ##################################
         4.5 MiB/s
done
Bytes transferred = 4310332 (41c53c hex)
## Copying 'firmware-1' subimage from FIT image at 90000000 ...
md5+ sha1+    Loading part 15 ... OK
DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

K2_BM_15. 07-nogit SoC:k2hk built:20:07:43, Sep 10 2020

## installed monitor @ 0xc5f0000, freq [203450520], status 207552512
## Copying 'fdt-2' subimage from FIT image at 90000000 ...
crc32+    Loading part 253 ... OK
## Copying 'kernel-1' subimage from FIT image at 90000000 ...
md5+ sha1+    Loading part 0 ... OK
## Loading kernel from FIT Image at 90000000 ...
   Using 'config-1' configuration
   Trying 'kernel-1' kernel subimage
     Description:  XXXX Kernel
     Created:      2020-09-22  19:35:05 UTC
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x900a1298
     Data Size:    3564032 Bytes = 3.4 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x80000000
     Entry Point:  0x80000000
     Hash algo:    md5
     Hash value:   c1254a24db7ddb1584c950d6a1a23907
     Hash algo:    sha1
     Hash value:   10983e72e01c411757da5e1c233c7fe1336b2e6a
   Verifying Hash Integrity ... md5+ sha1+ OK
## Flattened Device Tree blob at 81fe0000
   Booting using the fdt blob at 0x81fe0000
   Loading Kernel Image ... OK
   Loading Device Tree to 8fff2000, end 8ffff5f3 ... OK

Starting kernel ...

DEBUG: >>>> skern_poweron_cpu(1) >>>>

DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

DEBUG: >>>> skern_poweron_cpu(2) >>>>

DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

DEBUG: >>>> skern_poweron_cpu(3) >>>>

DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (xxxxx@pdaiaeth) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #153 SMP PREEMPT Tue Sep 22 21:31:41 CEST 2020
[    0.000000] CPU: ARMv7 Processor [412fc0f4] revision 4 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: XXXXXX board (Linux)
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] Switching physical address space to 0x800000000
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x000000081f800000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp-common-memory@81f800000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x000000087e400000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: Using PSCI v0.1 Function IDs from DT
[    0.000000] percpu: Embedded 16 pages/cpu @de593000 s35468 r8192 d21876 u65536
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 455040
[    0.000000] Kernel command line: console=ttyS0,115200n8 {mtdparts} rootwait=1 root=/dev/zero rw initrd=-,8M rootdelay=4 rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs2,2048
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 1760228K/1824768K available (8192K kernel code, 226K rwdata, 2412K rodata, 2048K init, 263K bss, 31772K reserved, 32768K cma-reserved, 1275904K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1038b00   ( 227 kB)
[    0.000000]        .bss : 0xc103a000 - 0xc107be28   ( 264 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000]  Tasks RCU enabled.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode

Instead if I configure the same U-Boot without its SPL and use the PDK MLO:

Board_init@115: OK

**** PDK SBL ****
SBL Revision: 01.00.09.02 (Sep 23 2020 - 17:33:22)
1.8
psc_get_domain_num: Module Number 0x00000006 Domain num 0x00000001
Begin parsing user application
set spiParams.bitRate = 8000000
try open flash 0x0000bb19

Inside Nor_spiReadId  manfID: 0x00000020 devID: 0x0000bb19
NOR_open OK
norInfo->deviceId: 47897
norInfo->manufacturerId: 32
norInfo->blockCnt: 512
norInfo->pageCnt: 256
norInfo->pageSize: 256
norInfo->busWidth: 8

Open OK
SBL_MulticoreImageParse@71: Called

SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc000000
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc0003c0
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc04f9b8
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc06ae40
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc06ae60
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc073d00
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07acf4
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07ad00
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc089048
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07c298
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc089078
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc08907c
Jumping to user application...


U-Boot 2019.01-svn10 (Sep 23 2020 - 13:54:30 +0200)

CPU: 66AK2Hx SR3.1 (XXX)
Model: XXXXXXX XXXXXX board (UBoot)
DRAM:  DDR3A memory bank [XXXX-K2H-2G1600SED]
DDR3 speed 1600
DRAM: 2 GiB (includes reported below)
2 GiB
***************************************************************
Relocation Offset is: f3f46000
Relocating to fff46000, new gd at fdf05ed8, sp at fdf05eb0
***************************************************************
usb dr_mode not found
NAND:  
Device found, Manufacturer ID: 0x2c, Chip ID: 0xb3
Micron MT29F8G16ADBDAH4
1024 MiB
Loading Environment from SPI Flash... spi_flash_std_probe: slave=fdf0bb98, cs=0
SF: Detected mt25qu256a with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
turn_off_all_dsps#34: Called disabling DSP
Net:   eth0: netcp@2000000, eth1: netcp@slave-1, eth2: netcp@slave-2, eth3: netcp@slave-3

Net IF Nr: 4
Hit any key to stop autoboot: 1 0

=> run bootcmd1 bootcmd2 bootcmd3 bootcmd4
ubi0: attaching mtd1
ubi0: scanning is finished
ubi0: attached mtd1 (name "ubifs2", size 200 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 1600, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 260444989
ubi0: available PEBs: 0, total reserved PEBs: 1600, PEBs reserved for bad PEB handling: 160
<DIR>        7392  Mon Apr 06 14:50:46 2020  bin
<DIR>         160  Mon Apr 06 14:50:46 2020  dev
<DIR>        6928  Sun Dec 16 04:29:50 2018  etc
<DIR>        7296  Tue May 19 16:59:35 2020  lib
<DIR>         232  Mon Apr 06 14:50:46 2020  mnt
<DIR>         224  Mon Apr 06 14:50:46 2020  opt
<DIR>         160  Mon Apr 06 14:50:47 2020  run
<DIR>         224  Mon Apr 06 14:50:47 2020  srv
<DIR>         160  Mon Apr 06 14:50:47 2020  tmp
<DIR>         160  Mon Apr 06 14:50:47 2020  sys
<DIR>         880  Sun Dec 16 04:29:50 2018  var
<DIR>         752  Mon Apr 06 14:50:48 2020  usr
<DIR>         488  Tue Sep 22 19:35:06 2020  boot
<DIR>         224  Mon Jun 01 13:01:10 2020  home
<LNK>          20  Mon Apr 06 14:50:49 2020  init
<DIR>         160  Mon Apr 06 14:50:47 2020  proc
<DIR>        7744  Mon Apr 06 14:50:47 2020  sbin
<DIR>         224  Sun Dec 16 04:29:49 2018  media
                0  Sun Dec 16 04:31:05 2018  forcefsck

netcp@2000000 Waiting for SGMII auto negotiation to complete. done
Using netcp@2000000 device
TFTP from server 192.168.111.150; our IP address is 192.168.111.11
Filename '/tftpboot/XXXXXXX_multi.itb'.
Load address: 0x90000000
Loading: #################################################################
         #################################################################
         #################################################################
         ########################################################
         623 KiB/s
done
Bytes transferred = 3683489 (3834a1 hex)
## Copying 'firmware-1' subimage from FIT image at 90000000 ...
md5+ sha1+    Loading part 15 ... OK
DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

K2_BM_15. 07-nogit SoC:k2hk built:20:07:43, Sep 10 2020

## installed monitor @ 0xc5f0000, freq [203450520], status 207552512
## Copying 'fdt-2' subimage from FIT image at 90000000 ...
crc32+    Loading part 253 ... OK
## Copying 'kernel-1' subimage from FIT image at 90000000 ...
md5+ sha1+    Loading part 0 ... OK
## Loading kernel from FIT Image at 90000000 ...
   Using 'config-1' configuration
   Trying 'kernel-1' kernel subimage
     Description:  XXXX Kernel
     Created:      2020-09-23  12:05:56 UTC
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x90008230
     Data Size:    3564032 Bytes = 3.4 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x80000000
     Entry Point:  0x80000000
     Hash algo:    md5
     Hash value:   c1254a24db7ddb1584c950d6a1a23907
     Hash algo:    sha1
     Hash value:   10983e 72e01c411757da5e1c233c7fe1336b2e6a
   Verifying Hash Integrity ... md5+ sha1+ OK
## Flattened Device Tree blob at 81fe0000
   Booting using the fdt blob at 0x81fe0000
   Loading Kernel Image ... OK
   Loading Device Tree to 8fff2000, end 8ffff5f3 ... OK

Starting kernel ...  <<<< remain stop here (no ARM 1-3 are activated)

The same problem if I use a VxWorks application (this is a client request, but I suppose
here is also other problem to solve below):

Board_init@115: OK

**** PDK SBL ****
SBL Revision: 01.00.09.02 (Sep 23 2020 - 17:33:22)
1.8
psc_get_domain_num: Module Number 0x00000006 Domain num 0x00000001
Begin parsing user application
set spiParams.bitRate = 8000000
try open flash 0x0000bb19

Inside Nor_spiReadId  manfID: 0x00000020 devID: 0x0000bb19
NOR_open OK
norInfo->deviceId: 47897
norInfo->manufacturerId: 32
norInfo->blockCnt: 512
norInfo->pageCnt: 256
norInfo->pageSize: 256
norInfo->busWidth: 8

Open OK
SBL_MulticoreImageParse@71: Called

SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc000000
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc0003c0
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc04f9b8
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc06ae40
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc06ae60
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc073d00
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07acf4
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07ad00
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc089048
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc07c298
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc089078
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc08907c
Jumping to user application...


U-Boot 2019.01-svn10 (Sep 23 2020 - 13:54:30 +0200)

CPU: 66AK2Hx SR3.1 (XXXX)
Model: XXXXXXXXX board (UBoot)
DRAM:  DDR3A memory bank [XXXX-K2H-2G1600SED]
DDR3 speed 1600
DRAM: 2 GiB (includes reported below)
2 GiB
***************************************************************
Relocation Offset is: f3f46000
Relocating to fff46000, new gd at fdf05ed8, sp at fdf05eb0
***************************************************************
usb dr_mode not found
NAND:  
Device found, Manufacturer ID: 0x2c, Chip ID: 0xb3
Micron MT29F8G16ADBDAH4
1024 MiB
Loading Environment from SPI Flash... spi_flash_std_probe: slave=fdf0bb98, cs=0
SF: Detected mt25qu256a with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
turn_off_all_dsps#34: Called disabling DSP
Net:   eth0: netcp@2000000, eth1: netcp@slave-1, eth2: netcp@slave-2, eth3: netcp@slave-3

Net IF Nr: 4
Hit any key to stop autoboot: 1 0

=> run boot_vx

netcp@2000000 Waiting for SGMII auto negotiation to complete. done
Using netcp@2000000 device
TFTP from server 192.168.111.150; our IP address is 192.168.111.11
Filename '/tftpboot/XXXX/uVxWorks'.
Load address: 0x82000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #######
         3.2 MiB/s
done
Bytes transferred = 6768524 (67478c hex)

netcp@2000000 Waiting for SGMII auto negotiation to complete. done
Using netcp@2000000 device
TFTP from server 192.168.111.150; our IP address is 192.168.111.11
Filename '/tftpboot/xxxx/k2hk_xxxx.dtb'.
Load address: 0x88000000
Loading: #
         1.7 MiB/s
done
Bytes transferred = 7003 (1b5b hex)
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   vxworks
   Created:      2020-09-08  14:09:17 UTC
   Image Type:   ARM VxWorks Kernel Image (uncompressed)
   Data Size:    6768460 Bytes = 6.5 MiB
   Load Address: 80100000
   Entry Point:  80100000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Kernel Image ... OK
   Loading Device Tree to 8fffb000, end 8ffffb5a ... OK
## Starting vxWorks at 0x80100000, device tree at 0x8fffb000 ...
initialize CPU
start CPU
initialize MMU
initialize base virtual memory support
initialize virtual memory support module
initialize address space library
initialize global mapping
initialize VxBus
        install bus types:
                vxbMiiBus(MII bus type)
                vxbFdtBus(Flattened Device Tree bus type)
                vxbNexusBus(Nexus bus type)
        install drivers:
                armgic(ARM GIC FDT driver)
                armGenTimer(ARM Generic Timer)
                netcp(Ti keystone Netcp end driver in switch mode)
                keystone-fix-clock(TI Keystone fix rate clock FDT driver)
                keystone-main-pll-clock(TI Keystone main pll clock FDT driver)
                keystone-pll-divder-clock(TI Keystone pll divider clock FDT driver)
                keystone-fix-factor-clock(TI Keystone fix factor clock FDT driver)
                keystone-power-module-clock(TI Keystone power module clock FDT driver)
                ksTimer(TI keystone 64-bit timer)
                genericPhy(Generic 10/100/1000 PHY driver)
                fdtBus(FDT bus controller)
                simpleBus(simple bus controller)
                ns16550(ns16550 serial OF driver)
                mainbus(Generic Root Nexus Driver)
        probe and attach devices
------------------------------------AFI_DEBUG_20200908 vxbLibInit() START
                probe mainbus
                attach mainbus:0
                probe fdtBus
                attach fdtBus:0
                probe soc
                attach simpleBus:0
                probe refclksys
                attach keystone-fix-clock:0
                probe mainpllclk
                attach keystone-main-pll-clock:0
                probe mainplldiv1
                attach keystone-pll-divder-clock:0
                probe internaldiv_6
                attach keystone-fix-factor-clock:0
                probe sharedlocaldiv_6
                attach keystone-fix-factor-clock:1
                probe interrupt-controller
                attach armgic:0
                probe timer0
                attach ksTimer:0
                probe timer1
                attach ksTimer:1
                probe timer2
                attach ksTimer:2
                probe generic-timer
                attach armGenTimer:0
                probe i2c
                failed to probe i2c
                probe serial0
                attach ns16550:0
                probe gpio
                failed to probe gpio
                probe edma0
                failed to probe edma0
                probe edma1
                failed to probe edma1
                probe edma2
                failed to probe edma2
                probe edma3
                failed to probe edma3
                probe edma4
                failed to probe edma4
                probe netcp_ethernet_sw
                attach netcp:0
                probe netcp_ethernet_ip
                failed to probe netcp_ethernet_ip
                probe cpus
                failed to probe cpus
                probe virtBus
                failed to probe virtBus
------------------------------------AFI_DEBUG_20200908 vxbLibInit() OK
------------------------------------AFI_DEBUG_20200908 cpcInit() START
------------------------------------AFI_DEBUG_20200908 cpcInit() vxIpiConnect = OK
------------------------------------AFI_DEBUG_20200908 cpcInit() vxIpiEnable(0) = OK
------------------------------------AFI_DEBUG_20200908 vxdbgCpuLibInit() START      <<<< VxWorks stop here.

If use TI boot-monitor VxWorks stops early:

....
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   vxworks
   Created:      2020-09-08  14:09:17 UTC
   Image Type:   ARM VxWorks Kernel Image (uncompressed)
   Data Size:    6768460 Bytes = 6.5 MiB
   Load Address: 80100000
   Entry Point:  80100000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Kernel Image ... OK
   Loading Device Tree to 8fffb000, end 8ffffb5a ... OK
## Starting vxWorks at 0x80100000, device tree at 0x8fffb000 ...  <<<< VxWorks stop here.

I suppose that Linux is not able to activate the slave ARMs and remain in waiting phase.
The question is which code is missing in MLO to activate that cores?

PS: U-Boot start only on ARM Core0.

Now this MLO is able to start an alone U-Boot, a couple of DSPs (core0&1) or U-Boot+DSP

Board_init@115: OK

**** PDK SBL ****
SBL Revision: 01.00.09.02 (Sep 23 2020 - 16:31:56)
1.8
Begin parsing user application
set spiParams.bitRate = 8000000
try open flash 0x0000bb19

Inside Nor_spiReadId  manfID: 0x00000020 devID: 0x0000bb19
NOR_open OK
norInfo->deviceId: 47897
norInfo->manufacturerId: 32
norInfo->blockCnt: 512
norInfo->pageCnt: 256
norInfo->pageSize: 256
norInfo->busWidth: 8

Open OK
SBL_MulticoreImageParse@71: Called

SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x8003a0
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc0f4200
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc224458
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc1fae40
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc223d00
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x800200
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x80031c
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x80033c
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x800500
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x830000
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x834200
SBL_RprcImageParse@366: DSP0 L2SRAM DestAddr 0x800000
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc211b80
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc1a6060
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x8003a0
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc0f4200
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc224458
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc1fae40
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc223d00
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x800200
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x80031c
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x80033c
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x800500
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x830000
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x834200
SBL_RprcImageParse@366: DSP1 L2SRAM DestAddr 0x800000
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc211b80
SBL_RprcImageParse@353: MSMCSRAM DestAddr 0xc1a6060
Jumping to user application...
No ARM application defiPlatformInit Done...
ne
XXXX Test SW Ver 0.0.1 Build 42 CPU Freq 983 MHz DSP's Core0 Cores 8
DSP hw rev. 0 DSP name "TMS320C66AK2H14" Board Name XXXXX" build date Sep 23 2020 16:28:00
....

Are you some suggestion to solve this problem?

Regards,
Dario

  • 0
    TI__Guru 50170 points

    HI, Dario,

    That's quite a long logs. I need to go through them slowly. I will get back to you after I walk through your logs.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex.

      no problem.

    I have added some printout before uboot jumps in linux and at the first functions in linux.
    Seems that's no start linux:

    ## Flattened Device Tree blob at 81fe0000
       Booting using the fdt blob at 0x81fe0000
       Loading Kernel Image ... OK
    flush_dcache_range@183: End
    do_bootm_linux@416:Called
    do_bootm_linux@423:0.0
       Loading Device Tree to 8fff2000, end 8ffff5f3 ... OK
    do_bootm_linux@425:0.1
    do_bootm_linux@416:Called
    do_bootm_linux@430:1.0
    ## Transferring control to Linux (at address 80000000)...

    Starting kernel ...

    cleanup_before_linux@84:Called
    cleanup_before_linux_select@28:Called
    dcache_disable@360: Called
    v7_outer_cache_disable@229:Called
    invalidate_dcache_all@171: End
    icache_disable@339: Called
    cache_disable@288: Called
    cache_disable@308: End
    icache_disable@341: End
    invalidate_icache_all@203: Called
    invalidate_icache_all@218: End
    cpu_cache_initialization@24:Called
    announce_and_cleanup@113:Called
    boot_jump_linux@400:1  <<<< remain stop here

    The latest printout is:

    static void boot_jump_linux(bootm_headers_t *images, int flag)
    {

    ....

        if (!fake) {
    #ifdef CONFIG_ARMV7_NONSEC
            if (armv7_boot_nonsec()) {
                armv7_init_nonsec();
                secure_ram_addr(_do_nonsec_entry)(kernel_entry,
                                  0, machid, r2);
            } else
    #endif
                printk("%s@%d:1 \n", __func__, __LINE__); <<<<<< here
                kernel_entry(0, machid, r2); <<<< here linux is run (I think)
        }
    #endif
        printk("%s@%d:End \n", __func__, __LINE__);
    }

    In uboot I have added a printout in every function in cache_v7.c, in cpu.c and in cache-cp15.c, etc
    In linux I have added a printout in every function in setup.c and in main.c.

    If use SPL instead:

    ## Flattened Device Tree blob at 81fe0000
       Booting using the fdt blob at 0x81fe0000
       Loading Kernel Image ... OK
    flush_dcache_range@183: End
    do_bootm_linux@416:Called
    do_bootm_linux@423:0.0
       Loading Device Tree to 8fff2000, end 8ffff5f3 ... OK
    do_bootm_linux@425:0.1
    do_bootm_linux@416:Called
    do_bootm_linux@430:1.0
    ## Transferring control to Linux (at address 80000000)...

    Starting kernel ...

    cleanup_before_linux@84:Called
    cleanup_before_linux_select@28:Called
    dcache_disable@360: Called
    v7_outer_cache_disable@229:Called
    invalidate_dcache_all@171: End
    icache_disable@339: Called
    cache_disable@288: Called
    cache_disable@308: End
    icache_disable@341: End
    invalidate_icache_all@203: Called
    invalidate_icache_all@218: End
    cpu_cache_initialization@24:Called
    announce_and_cleanup@113:Called
    boot_jump_linux@400:1
    DEBUG: >>>> skern_poweron_cpu(1) >>>>

    DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

    DEBUG: >>>> skern_poweron_cpu(2) >>>>

    DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

    DEBUG: >>>> skern_poweron_cpu(3) >>>>

    DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz
    [    0.000000] start_kernel@553:Called
    [    0.000000] smp_setup_processor_id@611:Called
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.14.79-gbde58ab01e (inddaia@pdaiaeth) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #157 SMP PREEMPT Thu Sep 24 01:35:19 CEST 2020
    [    0.000000] setup_arch@1110:Called
    [    0.000000] setup_processor@699:Called
    [    0.000000] __get_cpu_architecture@248:Called
    [    0.000000] cpu_architecture@280:Called
    [    0.000000] CPU: ARMv7 Processor [412fc0f4] revision 4 (ARMv7), cr=30c5387d

    Seems that the boot-monitor is not called or is no answer (loop) or is not able to activate ARM cores.

    Regards,
    Dario

  • 0 in reply to dario iannaccio
    Intellectual 870 points

    Hi,

      Little update.


    In sbl_slave.c I have seen the following macros:

    /* RBL address for ARM entry */
    #define ARM_MAGIC_ADDRESS   0x0C5AD000
    /* SBL address for ARM subcore entry */
    #define SBL_ARM_MAGIC       0x0C0FFF00

    Are these addresses correct for K2H?

    There are not description for that addresses (I didn't find them), anyway I have moved in 0x0C0C0000
    the MLO, in 0x0C000000 I have uboot, at 0x0C5F0000 the boot monitor, in 0xC0F0000 I have
    placed my DSP application.
    The other addresses in MSMCSRAM are used for DSP sharing data from DSPs o for DSP&ARM.

    Regards,
    Dario


  • 0 in reply to dario iannaccio
    TI__Guru 50170 points

    Hi, Dario,

    In your boot logs, I saw you have "run ubiUpgrade" to burn image to NAND. Is that image later also used in the scenario of booting DSP?  I am not familiar with the .itb usage and assume it is the device tree blob for the kernel(?). So the kernel is not using dtb file in /boot of the filesystem? 

    In the boot logs of loading DSP application, there are some discrepancies comparing to those without loading DSP.  Loading MLO first, the kernel boot logs do not show “volume 0 ("rootfs") re-sized from 1009 to 1436 LEBs”.  I am not sure if it is significant, may be it should be looked at. Also why the sizes of some directories are different between 2 boots if they are using the same filesystem in NAND? The size of .itb files between 2 boots are also different, are they supposed to be? In the logs, the Data Start addresses are different too. These probably need to understand to see if they have any impact.

    I am not expert on booting DSP images or on DSP operation. I'll need to loop in my coworker to see if he has any comments.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex.

    ************* Update info *********************

    The NAND FS is used ony from linux, no DSP use it, the uBoot DTB is stored inside U-Boot.

    In ITB file I have a uboot copy (used for on board uboot upgrade), the boot-monitor, a kernel
    and a couple DTBs (one for EVM environment, not used now, and the second one for custom
    board), in ITB now I haven't stored inetrd file (in previous I have used it).

    In linux kernel I have insert also netcp and xnetcp TI fw drivers, marvel10 fw driver for 3310
    and others FWs.

    The NAND FS arago-base-tisdk-image-k2hk-evm.tar.xz is decompress and
    customized with my linux drivers and some other script to configure all eth interfaces
    and others thing.

    ************************** Question: ******************

    The boot-monitor callback used to activate additional ARM are called from uboot or from linux?

    I have seen that uboot print latest printout before leave the control to linux, after some seconds
    (4~5) (when works) I can see the ARM activation print, then I suppose is linux that send a
    message (or IRQ, I don't know). I think the print appears after that the core is activated without
    attempts (or counter) then the infinite loop when not works.

    Other possibility that the SPL in uboot have the correct function/procedure to able the ARMs
    that function is not definet (or not well done) in MLO.

    PS: But the assembler is a bit ostic for me.


    For test purpose yesterday I have done some test using the uboot command to mon_power, if
    boot-monitor is not loaded the power on/off blocks uboot (now uboot is loaded using SPL):

    => mon_power
    mon_power - Power On/Off secondary core

    Usage:
    mon_power mon_power <coreid> <oper>
    - coreid (1-3) and oper (1 - ON, 0 - OFF)

    => mon_power 1 0
    mon_power_off@56: Called   <<<< blocked here

    The behaviour seems the same of MLO scenario.
    If the monitor is loaded instead:

    => run bootcmd1 bootcmd2 bootcmd3
    ubi0: attaching mtd1
    ubi0: scanning is finished
    ubi0: attached mtd1 (name "ubifs2", size 200 MiB)
    ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
    ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
    ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
    ubi0: good PEBs: 1600, bad PEBs: 0, corrupted PEBs: 0
    ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
    ubi0: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 2093418666
    ubi0: available PEBs: 0, total reserved PEBs: 1600, PEBs reserved for bad PEB handling: 160
    ....

    netcp@2000000 Waiting for SGMII auto negotiation to complete. done
    Using netcp@2000000 device
    TFTP from server 192.168.111.150; our IP address is 192.168.111.23
    Filename '/tftpboot/DRSP/DRSP_multi.itb'.
    Load address: 0x90000000
    Loading: #################################################################
             #################################################################
             #################################################################
             #################################################################
             ##################################
             51.8 KiB/s
    done
    Bytes transferred = 4312788 (41ced4 hex)
    ## Copying 'firmware-1' subimage from FIT image at 90000000 ...
    md5+ sha1+    Loading part 15 ... OK
    flush_dcache_range@183: End
    mon_install@18: Called
    DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz

    K2_BM_15. 07-nogit SoC:k2hk built:20:07:43, Sep 10 2020

    ## installed monitor @ 0xc5f0000, freq [203450520], status 207552512
    ## Copying 'fdt-2' subimage from FIT image at 90000000 ...
    crc32+    Loading part 253 ... OK
    flush_dcache_range@183: End
    ## Copying 'kernel-1' subimage from FIT image at 90000000 ...
    md5+ sha1+    Loading part 0 ... OK
    flush_dcache_range@183: End
    => mon_power 1 0
    mon_power_off@56: Called
    DEBUG: >>>> skern_poweroff_cpu(1) >>>>

    core 1 powered off successfully

    => mon_power 1 1
    mon_power_on@37: Called
    DEBUG: >>>> skern_poweron_cpu(1) >>>>

    core 1 powered on successfully
    => DEBUG: Message2 from Secure Mode: Core freq - 203450520Hz


    The scripts bootcmd1 bootcmd2 bootcmd3 downloads ITB file and decompress
    all modules inside and load boot-monitor.
    I remember you that when yesterday I had attempt to start linux (after MLO/U-Boot)
    I have also load boot-monitor (I am not remember if I had used or not mon_power
     command).



    *************************** Answer ********************

    I am not use the /boot direcory in NAND (now), when the system will to be stable I can use it
    (to avoid to continue NAND downaload), anyway the rootfs is loaded later.

    The difference size of multi.itb (-600kB)  is caused from removing uboot from ITB (becouse
    upgrade uboot.gph is not usable in MLO scenario).

    VxWorks starts in a different address in DDR3A (0x80100000) respect my linux kernel
    0x80000000, but in MLO/SPL the address are the same (I have interpretate well your question?).

    The NAND in custom board is double respect the NAND in EVM (1GBytes) and I think I have
    done some mistake in parameter in mtdpart (I will check soon, thanks).


    Thank you for your support.


    Regards,
    Dario

  • 0 in reply to dario iannaccio
    TI__Guru 50170 points

    Hi, Dario,

    Sorry for the slow response. I'll need my coworker to take a look at this. He may have some insight on the MLO boot DSP prior to Linux boot.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex,

        thank you again.

    Regards,
    Dario

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex,

       have you any news about this problem?

    Regards
    Dario

  • 0 in reply to dario iannaccio
    TI__Guru 50170 points

    Hi, Dario,

    I haven't heard back from my coworker. I'll ping him again.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex,

        today I have done another test. I have configured linux to run on a single Core and MLO is able to start it. Then I suppose the problem is related ad SMP mode (activation of secondary cores).

    Thank you for your support.

    Dario

  • 0 in reply to dario iannaccio
    TI__Guru 50170 points

    Hi, Dario,

    Could you do the SMP mode boot and attach the full boot logs with and without the MLO download? I went back to your logs but none of the logs is long enough to see if any messages regarding the secondary cores which I show them below. Please attach the logs as files which will be easier to read and not overwhelming the post. Thanks!

    [ 0.001098] CPU: Testing write buffer coherency: ok
    [ 0.001125] CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
    [ 0.001330] /cpus/cpu@0 missing clock-frequency property
    [ 0.001356] /cpus/cpu@1 missing clock-frequency property
    [ 0.001382] /cpus/cpu@2 missing clock-frequency property
    [ 0.001408] /cpus/cpu@3 missing clock-frequency property
    [ 0.001417] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [ 0.039983] Setting up static identity map for 0x80200000 - 0x80200138
    [ 0.059987] Hierarchical SRCU implementation.
    [ 0.080148] EFI services will not be available.
    [ 0.100035] smp: Bringing up secondary CPUs ...
    [ 0.175032] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [ 0.175039] CPU1: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
    [ 0.245132] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
    [ 0.245139] CPU2: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
    [ 0.315225] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
    [ 0.315231] CPU3: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
    [ 0.315364] smp: Brought up 1 node, 4 CPUs
    [ 0.315374] SMP: Total of 4 processors activated (1600.00 BogoMIPS).
    [ 0.315381] CPU: All CPU(s) started in HYP mode.
    [ 0.315388] CPU: Virtualization extensions available.
    [ 0.315850] devtmpfs: initialized
    [ 0.321841] random: get_random_u32 called from bucket_table_alloc+0x104/0x22c with crng_init=0

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex,

         thank you for your help, to solve this big problem (for us) I have done a workaround.

    The SCI interface is not working, RPC is not handled in VxWorks or in u-boot, vxworks start from
    uboot only.... too many problem to solve quickly.

    I have ported some functions from MLO in uboot and I have added a new command to parse RPRC
    file and it copy the memory sections in DSP/MSMC memory, after that I have relased the reset of
    choised DSPs.

    The only problem that I have seen is related at DSP power on from power down state, in fact I had to
    disabled the DSP power down function (replaced with a stub) and now the DSP boot in Uboot is
    obtained after restart from microcontroller or from OS command.

    To do that I have ported some .h file (from pdk). If do you want my files can you ask to me.

    PS: The TI documentation about PSC is terrible, on k2h datasheet exist only one doc related at PSC but
           it's for Keystone I, uboot touch some bits reserved (in docs) and the registers name are different.

    Eg:
    int psc_disable_domain(u32 domain_num)
    {
        u32 pdctl;
        u32 ptcmd;
                                  // no status check is done before to use it (step 1 in 2.3.3)
        pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
        pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF); // bit 0 PDCTL (NEXT field)
        pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP); // bit 12 &13 PDCTL (reserved)
        __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));

        ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
        ptcmd |= (u32)(1 << domain_num);   // go[x] bit
        __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);

        return psc_wait(domain_num);
    }

    Have you any updated PSC documentation related K2S? (I have consulted sprugv4c.pdf 9/2014)

    Regards,
    Dario

  • 0 in reply to dario iannaccio
    TI__Guru 50170 points

    Hi, Dario,

    The PSC User's Guide works for both KS-1 and KS-2, There isn't any updated version of the PSC UG, but it is interesting to see the code is setting bit 12-15. Let me check internally what it is based on.

    Rex

  • 0 in reply to Rex Chang
    TI__Guru 50170 points

    Hi, Dario,

    We can't find any document describing those reserved bit. We only use NEXT bit. Even in RTOS GEL file, it only use bit 0.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 870 points

    Hi Rex,

      Ok it is possible that bits will be not valid in K2H but for other TI architectures.

    In this doc I didn't see the additional needed step for DPS (place it inreset before to do a power down).


    Anyway now woks enought.

    Thank you.

    Regards,
    Dario