• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 97 subscribers
  • Views 358 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Queries related to SDMA

Girisha SG
Intellectual 970 points
Other Parts Discussed in Thread: OMAP3530

We are using OMAP3530 processor. I have created 2 SDMA channels and linked them in channel linking mode(i.e. channel A is connected to channel B and channel B is connected to channel A). I have set irqenable register for the channels that I have allocated. I am checking irqstatus register after every interrupt. Initially it is set only for channel A but whe channel B starts transfer it is set for both the channels & it continues in the same way (ofcourse we are resetting it after every interrupt)...

What is the problem and how can I resolve it ?

  • 0
    TI__Guru 64490 points

    It is a little confusing to understand what you expect and desire.  Perhaps you could clarify.

    If you have enabled each of the channels (both A and B) interrupt capability, it seems reasonable to me that you would receive an indication in the IRQSTATUS register for that channel (both A and B).  Why would you expect something differently?

    Each of the channels can have any number of possible events to cause an interrupt.  These are detailed in Table 9-8 of the OMAP3530 Technical Reference Manual.

  • 0 in reply to BrandonAzbell
    Intellectual 970 points

    I have created two channels for doing Ping-Pong transfer(i.e. One buffer will be with DMA & other will be getting filled by application). I have linked them using channel linking mechanism (by this I understand that only one channel will be active at any instant & DMA controller will transfer data from one buffer using one DMA channel at any point in time). If only one channel is active & doing the transfer only one bit should be set in 'irqstatus' register at any instant(We have heard the audio & it looks only one transfer is happening) but we are observing that bits for both the channels that we have created is getting set & hence we are not able to differentiate which channel has completed ... etc

  • 0 in reply to Girisha SG
    Intellectual 970 points

    I require SDMA driver that runs on OMAP3530 with Linux OS. Also I would highly appreciate if the code is using channel linking concept with 'irqenable' & 'irqstatus' SDMA registers(to take some sort of decission).