AM3352: possible SDRAM timing issue

Adam Kozlowski

Part Number: AM3352

Hi,

I've fabricated a custom board based on AM3352 and 128MB SDRAM (W631GU6MB-12). The PCB is designed according to 7.7.2.3 DDR3 and DDR3L Routing Guidelines from the datasheet.
Unfortunately, I have an issue while booting this custom board:
e2e.ti.com/.../3499621

There are two possible sources of this behavior:
1) U-boot configuration
2) SDRAM timing issue

ad 1)
I did almost everything to investigate this possible cause.
At this moment, I have no idea how I can investigate this further.
I have MLO and U-boot prepared. I use the same MLO and U-boot to boot BeagleBone Black (BBB as a reference test) and my custom board (GW3). BBB boots each time, while the custom board boots 1 per 3 attempts. Detailed description here: e2e.ti.com/.../3499621

ad 2)
I used the EMIF tool to prepare and verify (GEL script) the SDRAM.
I did a memory test using GEL script from EMIF tool. There were no errors detected.

Can I ask for a review of my EMIF spreadsheet:
2086.W631GU6MB_EMIF_Configuration.xlsx
Is it anything suspicious in it?

What can I do to find the source of this issue?
How can I investigate if it is the SDRAM issue?
How can I confirm that it relates to the SDRAM issue?

What are the recommended steps to troubleshoot this issue?

Regards
Adam

over 4 years ago

0 Brad Griffis over 4 years ago

TI__Guru*** 125430 points

Hi Adam,

Adam Kozlowski said:
I used the EMIF tool to prepare and verify (GEL script) the SDRAM.

Did you use the u-boot tab to update your u-boot files? Can you attach your board.c file for review?

Adam Kozlowski said:
What are the recommended steps to troubleshoot this issue?

Please download the following JTAG script:

http://git.ti.com/sitara-dss-files/am335x-dss-files/blobs/raw/master/am335x-ddr-analysis.dss

Directions on how to run it can be found here:

http://git.ti.com/sitara-dss-files/am335x-dss-files/blobs/master/README

Best regards,
Brad

0 Brad Griffis over 4 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

PS. I forgot to mention, please attach the output from the script (a *.txt file on your desktop) to this thread.

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Hi Brad,

Brad Griffis said:
Did you use the u-boot tab to update your u-boot files?

Yes, i did. Please find a board.c file attached.

Fullscreen 5775.board.c Download

// SPDX-License-Identifier: GPL-2.0+
/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <spl.h>
#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk_synthesizer.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/omap_mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
#include <environment.h>
// #include "../common/board_detect.h"
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
#define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
#define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

#define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
#define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)

#define GPIO0_IRQSTATUS1	(AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
#define GPIO1_IRQSTATUS1	(AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)

#define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
#define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)

#ifndef CONFIG_DM_SERIAL
struct serial_device *default_serial_console(void)
{
	return &eserial1_device;
}
#endif

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

static const struct ddr_data ddr3_beagleblack_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static const struct ddr_data ddr3_AM335xSKEVM_ddr_data = {
	.datardsratio0 =	0x00000040,
	.datawdsratio0 =	0x0000007C,
	.datafwsratio0 =	0x000000F3,
	.datawrsratio0 = 	0x000000BC,
};

static const struct cmd_control ddr3_AM335xSKEVM_cmd_ctrl_data = {
    .cmd0csratio = 	0x00000100,
    .cmd0iclkout = 	0x00000001,
    .cmd1csratio = 	0x00000100,
    .cmd1iclkout = 	0x00000001,
    .cmd2csratio = 	0x00000100,
    .cmd2iclkout = 	0x00000001,
};

static struct emif_regs ddr3_AM335xSKEVM_emif_reg_data = {
    .sdram_config = 	0x61A05232,
    .ref_ctrl = 	0x00000C30,
    .sdram_tim1 = 	0x0AAAD4DB,
    .sdram_tim2 = 	0x242F7FDA,
    .sdram_tim3 = 	0x50FFE2BF,
    .zq_config = 	0x500742C6,
    .emif_ddr_phy_ctlr_1 = 0x00100208,
};

const struct ctrl_ioregs ddr3_AM335xSKEVM_ioregs_data = {
    .cm0ioctl =	0x0000018B,
    .cm1ioctl =	0x0000018B,
    .cm2ioctl =	0x0000018B,
    .dt0ioctl =	0x0000018B,
    .dt1ioctl =	0x0000018B,
};

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
#ifdef CONFIG_SPL_SERIAL_SUPPORT
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;
#endif

#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_load();
	if (env_get_yesno("boot_os") != 1)
		return 1;
#endif

	return 0;
}
#endif

const struct dpll_params *get_dpll_ddr_params(void)
{
	int ind = get_sys_clk_index();
	return &dpll_ddr3_400MHz[ind];
}

const struct dpll_params *get_dpll_mpu_params(void)
{
	int ind = get_sys_clk_index();
	int freq = am335x_get_efuse_mpu_max_freq(cdev);

	switch (freq) {
	case MPUPLL_M_1000:
		return &dpll_mpu_opp[ind][5];
	case MPUPLL_M_800:
		return &dpll_mpu_opp[ind][4];
	case MPUPLL_M_720:
		return &dpll_mpu_opp[ind][3];
	case MPUPLL_M_600:
		return &dpll_mpu_opp[ind][2];
	case MPUPLL_M_500:
		return &dpll_mpu_opp100;
	case MPUPLL_M_300:
		return &dpll_mpu_opp[ind][0];
	}

	return &dpll_mpu_opp[ind][0];
}

static void scale_vcores_bone(int freq)
{
	int usb_cur_lim, mpu_vdd;

#ifndef CONFIG_DM_I2C
	if (i2c_probe(TPS65217_CHIP_PM))
		return;
#else
	if (power_tps65217_init(0))
		return;
#endif

	switch (freq) {
	case MPUPLL_M_1000:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
		break;
	case MPUPLL_M_800:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
		break;
	case MPUPLL_M_720:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
		break;
	case MPUPLL_M_600:
	case MPUPLL_M_500:
	case MPUPLL_M_300:
	default:
		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
		break;
	}

	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
			       TPS65217_POWER_PATH,
			       usb_cur_lim,
			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
		puts("tps65217_reg_write failure\n");

	/* Set DCDC3 (CORE) voltage to 1.10V */
	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
				    TPS65217_DCDC_VOLT_SEL_1100MV)) {
		puts("tps65217_voltage_update failure\n");
		return;
	}

	/* Set DCDC2 (MPU) voltage */
	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
		puts("tps65217_voltage_update failure\n");
		return;
	}

	/*
	 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
	 */
	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
			       TPS65217_DEFLS1,
			       TPS65217_LDO_VOLTAGE_OUT_1_8,
			       TPS65217_LDO_MASK))
		puts("tps65217_reg_write failure\n");

	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
			       TPS65217_DEFLS2,
			       TPS65217_LDO_VOLTAGE_OUT_3_3,
			       TPS65217_LDO_MASK))
		puts("tps65217_reg_write failure\n");
}

void gpi2c_init(void)
{
	/* When needed to be invoked prior to BSS initialization */
	static bool first_time = true;

	if (first_time) {
		enable_i2c0_pin_mux();
#ifndef CONFIG_DM_I2C
		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
			 CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
		first_time = false;
	}
}

void scale_vcores(void)
{
	int freq;

	gpi2c_init();
	freq = am335x_get_efuse_mpu_max_freq(cdev);
	scale_vcores_bone(freq);
}

void set_uart_mux_conf(void)
{
#if CONFIG_CONS_INDEX == 1
	enable_uart0_pin_mux();
#elif CONFIG_CONS_INDEX == 2
	enable_uart1_pin_mux();
#elif CONFIG_CONS_INDEX == 3
	enable_uart2_pin_mux();
#elif CONFIG_CONS_INDEX == 4
	enable_uart3_pin_mux();
#elif CONFIG_CONS_INDEX == 5
	enable_uart4_pin_mux();
#elif CONFIG_CONS_INDEX == 6
	enable_uart5_pin_mux();
#endif
}

void set_mux_conf_regs(void)
{
	enable_board_pin_mux();
}

const struct ctrl_ioregs ioregs_evmsk = {
	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
};

const struct ctrl_ioregs ioregs_bonelt = {
	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
};

const struct ctrl_ioregs ioregs_evm15 = {
	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
};

const struct ctrl_ioregs ioregs = {
	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
};

void sdram_init(void)
{
/*
 * Gateway3
 */
	config_ddr(400,
		&ddr3_AM335xSKEVM_ioregs_data,
		&ddr3_AM335xSKEVM_ddr_data,
		&ddr3_AM335xSKEVM_cmd_ctrl_data,
		&ddr3_AM335xSKEVM_emif_reg_data,0);
/*
 * BeagleBone Black
 */
//	config_ddr(400, 
//		&ioregs_bonelt,
//		&ddr3_beagleblack_data,
//		&ddr3_beagleblack_cmd_ctrl_data,
//		&ddr3_beagleblack_emif_reg_data, 0);
}
#endif

#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
static void request_and_set_gpio(int gpio, char *name, int val)
{
	int ret;

	ret = gpio_request(gpio, name);
	if (ret < 0) {
		printf("%s: Unable to request %s\n", __func__, name);
		return;
	}

	ret = gpio_direction_output(gpio, 0);
	if (ret < 0) {
		printf("%s: Unable to set %s  as output\n", __func__, name);
		goto err_free_gpio;
	}

	gpio_set_value(gpio, val);

	return;

err_free_gpio:
	gpio_free(gpio);
}

#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
#define REQUEST_AND_CLR_GPIO(N)	request_and_set_gpio(N, #N, 0);

#endif

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
	defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)

#define MAX_CPSW_SLAVES	2

/* At the moment, we do not want to stop booting for any failures here */
int ft_board_setup(void *fdt, bd_t *bd)
{
	const char *slave_path, *enet_name;
	int enetnode, slavenode, phynode;
	struct udevice *ethdev;
	char alias[16];
	u32 phy_id[2];
	int phy_addr;
	int i, ret;

	goto done;

	for (i = 0; i < MAX_CPSW_SLAVES; i++) {
		sprintf(alias, "ethernet%d", i);

		slave_path = fdt_get_alias(fdt, alias);
		if (!slave_path)
			continue;

		slavenode = fdt_path_offset(fdt, slave_path);
		if (slavenode < 0)
			continue;

		enetnode = fdt_parent_offset(fdt, slavenode);
		enet_name = fdt_get_name(fdt, enetnode, NULL);

		ethdev = eth_get_dev_by_name(enet_name);
		if (!ethdev)
			continue;

		phy_addr = cpsw_get_slave_phy_addr(ethdev, i);

		/* check for phy_id as well as phy-handle properties */
		ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
						 phy_id, 2);
		if (ret == 2) {
			if (phy_id[1] != phy_addr) {
				printf("fixing up phy_id for %s, old: %d, new: %d\n",
				       alias, phy_id[1], phy_addr);

				phy_id[0] = cpu_to_fdt32(phy_id[0]);
				phy_id[1] = cpu_to_fdt32(phy_addr);
				do_fixup_by_path(fdt, slave_path, "phy_id",
						 phy_id, sizeof(phy_id), 0);
			}
		} else {
			phynode = fdtdec_lookup_phandle(fdt, slavenode,
							"phy-handle");
			if (phynode < 0)
				continue;

			ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
			if (ret < 0)
				continue;

			if (ret != phy_addr) {
				printf("fixing up phy-handle for %s, old: %d, new: %d\n",
				       alias, ret, phy_addr);

				fdt_setprop_u32(fdt, phynode, "reg",
						cpu_to_fdt32(phy_addr));
			}
		}
	}

	done:
	return 0;
}

#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
	hw_watchdog_init();
#endif

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
	gpmc_init();
#endif

#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
#endif

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	struct udevice *dev;
#if !defined(CONFIG_SPL_BUILD)
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
//	char *name = NULL;

//	name = "BBEN";
//	set_board_info_env(name);

	/*
	 * Default FIT boot on HS devices. Non FIT images are not allowed
	 * on HS devices.
	 */
	if (get_device_type() == HS_DEVICE)
		env_set("boot_fit", "1");
#endif

#if !defined(CONFIG_SPL_BUILD)
	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

	if (!env_get("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ethaddr(mac_addr))
			eth_env_set_enetaddr("ethaddr", mac_addr);
	}

	mac_lo = readl(&cdev->macid1l);
	mac_hi = readl(&cdev->macid1h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

	if (!env_get("eth1addr")) {
		if (is_valid_ethaddr(mac_addr))
			eth_env_set_enetaddr("eth1addr", mac_addr);
	}

#endif

	if (!env_get("serial#")) {
		char *board_serial = env_get("board_serial");
		char *ethaddr = env_get("ethaddr");

		if (!board_serial || !strncmp(board_serial, "unknown", 7))
			env_set("serial#", ethaddr);
		else
			env_set("serial#", board_serial);
	}

	/* Just probe the potentially supported cdce913 device */
	uclass_get_device(UCLASS_CLK, 0, &dev);

	return 0;
}
#endif

/* CPSW platdata */
#if !CONFIG_IS_ENABLED(OF_CONTROL)
struct cpsw_slave_data slave_data[] = {
	{
		.slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
		.sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
		.phy_addr       = 0,
	},
	{
		.slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
		.sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
		.phy_addr       = 1,
	},
};

struct cpsw_platform_data am335_eth_data = {
	.cpsw_base		= CPSW_BASE,
	.version		= CPSW_CTRL_VERSION_2,
	.bd_ram_ofs		= CPSW_BD_OFFSET,
	.ale_reg_ofs		= CPSW_ALE_OFFSET,
	.cpdma_reg_ofs		= CPSW_CPDMA_OFFSET,
	.mdio_div		= CPSW_MDIO_DIV,
	.host_port_reg_ofs	= CPSW_HOST_PORT_OFFSET,
	.channels		= 8,
	.slaves			= 2,
	.slave_data		= slave_data,
	.ale_entries		= 1024,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= 0x20,
	.active_slave		= 0,
	.mdio_base		= 0x4a101000,
	.gmii_sel		= 0x44e10650,
	.phy_sel_compat		= "ti,am3352-cpsw-phy-sel",
	.syscon_addr		= 0x44e10630,
	.macid_sel_compat	= "cpsw,am33xx",
};

struct eth_pdata cpsw_pdata = {
	.iobase = 0x4a100000,
	.phy_interface = 0,
	.priv_pdata = &am335_eth_data,
};

U_BOOT_DEVICE(am335x_eth) = {
	.name = "eth_cpsw",
	.platdata = &cpsw_pdata,
};
#endif

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	return 0;
}
#endif

#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
	secure_boot_verify_image(p_image, p_size);
}
#endif

#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
	.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
	.cfg.f_min = 400000,
	.cfg.f_max = 52000000,
	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

U_BOOT_DEVICE(am335x_mmc0) = {
	.name = "omap_hsmmc",
	.platdata = &am335x_mmc0_platdata,
};

static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
	.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
	.cfg.f_min = 400000,
	.cfg.f_max = 52000000,
	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

U_BOOT_DEVICE(am335x_mmc1) = {
	.name = "omap_hsmmc",
	.platdata = &am335x_mmc1_platdata,
};
#endif

Brad Griffis said:
Please download the following JTAG script

See results:

Fullscreen am335x-ddr-analysis_2020-10-13_141607.txt Download

Switched to DAP_DebugSS
Read value of 2b94402e from Device_ID register.
Skipping read of EMIF registers since EMIF clock disabled.
 * EMIF registers are not readable when in DS0 state
 * If you are attempting to enter DS0 this is normal.
 * CM_PER_L3_CLKSTCTRL = 0000001a

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000004
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000004
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000004
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000004
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000004
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010107
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
  * CKE gated (forces pin low).

Regards

Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

Did your board attempt to boot before you ran the script? The output shows that the EMIF clock was never even turned on. It doesn't look like any of the EMIF configuration code has even attempted to run (or perhaps a reset occurred?). Does anything at all print to the console during this failed boot attempt? If you monitor nRESETIN_OUT do you see any resets? I think an easy way to see this would be to put a scope on it with falling edge trigger. It should not ever trigger because it should be low initially as the system powers up. Then it should transition high and stay high. If it ever goes low (falling edge) then something caused your device to reset.

Have you tried stepping through the u-boot code?

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Brad Griffis said:
Did your board attempt to boot before you ran the script?

I thought, the script has to be run alone.
Tomorrow, I'll perform this test again.

Brad Griffis said:
Does anything at all print to the console during this failed boot attempt?

Yes, it prints

U-Boot SPL 2019.01-gc14892445a-dirty (Oct 09 2020 - 13:38:40 +0200)
Trying to boot from MMC1


U-Boot 2019.01-gc14892445a-dirty (Oct 09 2020 - 13:38:40 +0200)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x Gateway3
DRAM:  128 MiB
MMC:   OMAP SD/MMC:
Loading Environment from FAT... oRR_VRRRRRRRR_RRRRRRRsRRRRp5** Invalid partition type �-Boot�" (expect "U-Boot")
<ethaddr> not set. Validating first E-fuse MAC
Net:   Could not get PHY for ethernet@4a100000: addr 0
eth0: ethernet@4a100000
Hit any key to stop autoboot:  0 
syntax error
=>

Brad Griffis said:
If you monitor nRESETIN_OUT do you see any resets?

The PORZ sequence is OK.
I ran this script without booting the board using the SD card.

To be clear...
Do I have to run this script, once I see the prompt from the u-boot?
or
Do I have to run this script, once the failed boot attempt?

Regards
Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

I recommend that you power on the board, press a key to halt at the u-boot prompt, and then run the script. Please post the resulting text file.

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Hi Brad,

Please, review the attached file:

Fullscreen am335x-ddr-analysis_2020-10-14_083058.txt Download

Switched to DAP_DebugSS
Read value of 2b94402e from Device_ID register.
CONTROL: device_id = 0x2b94402e
  * AM335x family
  * Silicon Revision 2.1

CONTROL: control_status = 0x00400338
  * SYSBOOT[15:14] = 01b (24 MHz)
CM_CLKSEL_DPLL_DDR = 0x00003202
  * DPLL_MULT = 50 (x50)
  * DPLL_DIV = 2 (/3)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 24 MHz
 -> CLKOUT_M2 = DDR_PLL_CLKOUT = 400 MHz

EMIF: SDRAM_CONFIG = 0x61a05232
  * Bits 31:29 (reg_sdram_type) set for DDR3
  * Bits 28:27 (reg_ibank_pos) set to 0
  * Bits 26:24 (reg_ddr_term) set for RZQ/4 (001b)
  * Bits 22:21 (reg_dyn_odt) DDR3 dynamic ODT set to RZQ / 4
  * Bit  20    (reg_ddr_disable_dll) set to 0, DDR3 DLL enabled
  * Bits 19:18 (reg_sdram_drive) set for RZQ/6 (00b)
  * Bits 17:16 (reg_cwl) set for 0, CWL = 5
  * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface
  * Bits 13:10 (reg_cl) set to 4 -> CL = 6
  * Bits 09:07 (reg_rowsize) set to 4 -> 13 row bits
  * Bits 06:04 (reg_ibank) set to 3 -> 8 banks
  * Bits 02:00 (reg_pagesize) set to 2 -> 10 column bits

EMIF: PWR_MGMT_CTRL = 0x00000000
 * Bits 10:8 reg_lp_mode set to 0, auto power management disabled
 * Warning: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
   -> Please see the silicon errata (DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit) for more details.
   -> This is only an issue if used in conjunction with reg_lp_mode=2.

DDR PHY: DDR_PHY_CTRL_1 = 0x00100208
  * Bits 9:8 (reg_phy_rd_local_odt) to 2 -> full thevenin termination
  * Bits 4:0 (reg_read_latency) set to 8 -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1.

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x61a05232
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x00000c30
*(0x4c000014) = 0x00000c30
*(0x4c000018) = 0x0aaad4db
*(0x4c00001c) = 0x0aaad4db
*(0x4c000020) = 0x242f7fda
*(0x4c000024) = 0x242f7fda
*(0x4c000028) = 0x50ffe2bf
*(0x4c00002c) = 0x50ffe2bf
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x0af26305
*(0x4c000084) = 0x0038beac
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0x7b297f0f
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x500742c6
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00100208
*(0x4c0000e8) = 0x00100208
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x0000018b
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x0000018b
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x0000018b
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x0000018b
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x0000018b
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew slow
    - Drive Strength 9 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew slow
    - Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010167
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
  * CKE controlled by EMIF (normal/ungated operation).

Regards

Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

Adam,

I've reviewed your spreadsheet as well as the output from the text file. Everything looks proper.

Adam Kozlowski said:
Loading Environment from FAT... oRR_VRRRRRRRR_RRRRRRRsRRRRp5** Invalid partition type �-Boot�" (expect "U-Boot")

What files do you have in your boot partition? Do you have a uEnv.txt? Based on the messages, I think there might be some kind of issue with the formatting of that file. Have you tried just deleting it completely? Are there boot settings you're specifically trying to override?

Best regards,
Brad

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Hi Brad,

Thanks for the review you did.

Brad Griffis said:
What files do you have in your boot partition?

I have two files: MLO and u-boot.img

Brad Griffis said:
Do you have a uEnv.txt?

No, I don't have.

Brad Griffis said:
Have you tried just deleting it completely?

Yes, I've tried even with different SD cards.

Brad Griffis said:
Are there boot settings you're specifically trying to override?

No there are no settings I overwrite. Everything is left on default settings.
Moreover, I use the same configuration to boot BBB (as a reference) and my custom board.
BBB boots each time and there are no strange characters, while my custom board boots 1 per 3 attempts and reads strange characters from memory.

My issue (from the U-boot point of view) is described here:

I've done the memory test included in the GEL script from the EMIF tool, but it passes successfully.

Is there anything else I can do to verify that it relates to the SDRAM timing issue?
Can you think of anything I can do to further diagnose my case?
From my perspective, the next step is a board redesigning.

Regards
Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

Adam Kozlowski said:
I've done the memory test included in the GEL script from the EMIF tool, but it passes successfully.

That's a good start. However, I definitely would prefer to perform a test on the memory at a time where you've had a bad boot.

Adam Kozlowski said:
Is there anything else I can do to verify that it relates to the SDRAM timing issue?

Try this:

Power up the board. I want to see a failed power-up, so if the first power-up succeeds, try again until there's a failure.
Connect with JTAG.
Open a memory window to address 0x80000000. Set the data size to 16 bit TI-style hex.
Maximize your memory window.
Hit refresh a bunch of times. Do you see anything turning red? CCS will mark any changes red when you refresh. If everything is working properly you shouldn't see any red.
Try poking some values into random locations of the memory. As you hit enter CCS will refresh the whole window so pay attention for anything else turning red.

This admittedly is far from a stress test. In other words, if this succeeds it doesn't necessarily mean your DDR is perfect. However, in most cases where there's a DDR issue, this test can usually turn up some problems. In any case, it's an easy test to perform, so definitely worth trying.

Adam Kozlowski said:
From my perspective, the next step is a board redesigning.

I expect we should be able to narrow down the problem. Hopefully a redesign won't be necessary, but if it is, we really need to understand what specifically you're fixing. A less invasive option might be to build a board with a different memory on it.

One other question... In the spreadsheet you filled out, I assume you populated the trace length info for the clock and DQS signals right? It looked like it was different than the defaults, and the values seemed reasonable. Having accurate trace lengths in that step is really important so I thought I would double check.

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Hi Brad,

I think I've found the issue.
The CLK_N and CLK_P traces were left unmatched to the rest of the address net class.
The guy who did the PCB design has to correct this.
See below.

Could this be the source of the problem in your opinion?

As usual, your expertise was incredibly helpful.
Thank you.

Regards
Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

I don't know if it is THE issue, but it's definitely an issue... CLK_N/P should be within 5 mils of one another. Also an issue is the fact that these clock signals are significantly shorter than the other address/control signals. The longest and shortest address/control/clock signals should be within 100 mils of one another.

Are you able to upload the full spreadsheet of trace lengths? Given the significant issues I've seen so far, there may very well be more.

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

Take a look: DDR_traces.xlsx

Every clock is matched separately and not within the class it belongs to. For sure, it must be corrected.

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

Agreed. The DQS_N/P signals need to be within 5 mils of one another (which they are). However, those signals should be within 25 mils of the other signals in that same byte lane. Furthermore all of the data signals should be within 25 mils of each other. At this point, I would agree with your earlier statement that you will need to revise the board.

FYI, one other thing you might consider trying is to drop the clock frequency for the DDR3 interface to 303 MHz. That's the lowest allowed speed due to DLL requirements. It is possible you might see better stability at that speed, perhaps enough to allow you to do a bit more bring-up to see if there are any other issues that need to be fixed. If you change the DPLL configuration as well as the refresh rate, that's sufficient to adjust the frequency (i.e. you don't need to reprogram every single register).

0 Adam Kozlowski over 4 years ago in reply to Brad Griffis

Expert 1805 points

That's my point exactly.
Thank you for the expertise you provided.

Regards
Adam

0 Brad Griffis over 4 years ago in reply to Adam Kozlowski

TI__Guru*** 125430 points

Adam,

Sure, glad to help. After you revise your board, be sure to update the trace lengths in your EMIF spreadsheet. Those updates will correspondingly impact the ddr3_AM335xSKEVM_ddr_data and ddr3_AM335xSKEVM_cmd_ctrl_data structures which you'll need to update in your code.

Best regards,
Brad

Processors

Processors forum

AM3352: possible SDRAM timing issue