Hi All,
I would like to ask some questions on DDR2 memory controller.
According to Spectrum EVM6437:
And according to Micron’s 512Mb: x4, x8, x16 DDR2 SDRAM:
The calculation above should be clearer than additional verbal description. We basically see that bank selection bits MUST be used to achieve the 128Mbytes memory, so the red-highlighted DDR_BA[2:0] should have been used.
But why table 2-14 of SPRS345d describe DDR_BA[2:0] as “required to support 1Gb DDR2”? I am finding this description a bit misleading because it is already in use with 128MBytes memory, not to mention 1Gb DDR2.
Does “b” here mean byte or bit? What is the convention here?
If it means byte, then the column address counter/latch should have 13bits input and feeds 11 of them to the column decoder. Is it correct?
And no matter 128Mbytes of DDR2 of the EVM or other sizes (including 1Gbytes above), there is no way that both the row address and the column address can be sent at one time by DDR_A[12:0], so they must be sent at different clock time, most likely in two times. Is this correct?
This is a bit new to me, but also seems reasonable. In principle and in the extreme, one address line at 32 times can send 32 bit address, so why not 13bits (DDR_A[12:0]) at two times for 23 (26, etc.) bits address?
So is this how DDR2 controller works? The memory-mapped (0x8000 0000 ~ 0x8FFF FFFF) logically address will be translated to DDR2 memory’s real address, then
1. BA[1:0] bank select could be sent at one time
2. Row and column address are sent at two times
to two DDR2 chips, and two 16-bit data will be combined to form an integral 32-bit data, either in reading or writing mode. Is this correct?
And it also seems to me that other controllers, be it FLASH or I2C, should all contain the same memory map translation module, and perhaps also fewer physical address lines than the logical number of address bits yet it could work in the same way as DDR2 controller by sending address over multiple times. Is this the way they work?
Thanks,
Zheng
