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DRA829V: False issue of nested IRQ interrupt

Rizwan Ahmad
Intellectual 676 points
Part Number: DRA829V
Other Parts Discussed in Thread: SYSBIOS

Hi,

  1. From IRQ interrupt another interrupt is triggered before VIM_STS register is cleared for current interrupt.
  2. Second interrupt is serviced and VIM_STS register is cleared (write 1 to clear) and VIM_IRQVEC register is also written to reprocess the interrupts, before entering the first interrupt handler.
  3. The first interrupt occurs again (IRQ exception) whereas it is expected to continue from the point where the higher priority IRQ interrupted the software.

However while during debugging it is noticed that if the code is stepped through VIM_STS and VIM_IRQVEC manipulation part for the higher priority interrupt, then the problem does not occur, but during free run the problem is reproducible.

Also, if the VIM_STS is cleared in the beginning of the first interrupt (before higher priority interrupt is triggered) then the issue is not reproduced.

Is a delay required after writing to the VIM registers? How to fix this issue?

Please advise.

Rizwan