Hello I state that I am on my first project in the HDMI field.
I would like to use tfp401 to receive a low or medium definition video stream to view it on a led screen.
Here the block diagram:
PC === (hdmi) ==> TFP401 == (parallel bus: RGB, Hsync, Vsync) ===> FPGA ======> LED PANNEL
At the moment I was unable to buy the TFP401PZP demoboard, so I'm using another one that looks like this "see Attachment"
TFP401 pin input configured as follows:
DFO = L
PD = open
PDO = open
ST = H
PIXS = L
STAG = H
OCK_INV = L
PC (raspberry PI-3) HDMI set like this: 800x480 65HZ or 640x480 60HZ
PROBLEMS and QUESTIONS:
1) why do the TFP401 Vsync Hsync pins give me unstable signals?
2) according to datasheet on page 15 "Table 2. TFP401 / 401A Modes of Operation" ODCK should work in "falling"
but pin switching (Hsync, Vsync, DE) also occurs without ODCK variations
3) according to datasheet on page 13 "Table 1. TMDS Pixel Data and Control Signal Encoding" DE (on ODCK front) can be used for
to discriminate valid RGB data from Hsync Vsync signals?
4) can you help me understand where where by misinterpreting the datasheet)
thank you
