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AM3356: CPU Clock Parent, U-Boot vs. Linux

Part Number: AM3356

According to our AM3356 efuses (0x44E10600 is 0x0001fef), it supports a CPU clock of 300MHz only. Our U-Boot and Linux configuration is based on the AM3356 EVM from the Arago Processor SDK. Looking at the U-Boot code, our board code uses the following MPU PLL configuration:

const struct dpll_params *get_dpll_mpu_params(void)
{
    int ind = get_sys_clk_index();
    int freq = am335x_get_efuse_mpu_max_freq(cdev);

    switch (freq) {
[...]
    case MPUPLL_M_300:
        return &dpll_mpu_opp[ind][0];
    }
[...]
}

const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
[...]
    {    /* 25 MHz */
        {24, 0, 2, -1, -1, -1, -1},    /* OPP 50 */
[...]

We can confirm that these are the PLL settings actually used (M2 = 2).

Question 1: What is the resulting CPU frequency? Is it 25MHz * 24 = 600MHz or 25MHz * 24 / 2 = 300MHz?

When Linux starts, it computes the CPU clock using MPU PLL N and M only (not M2) and assumes the CPU is running at 600MHz:

[    1.365424] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 600000 KHz

Question 2: Is it correct that Linux uses CPU clock "dpll_mpu_ck" as CPU clock source and not "dpll_mpu_m2_ck"?

Using our efuse value 0x0001fef, the only compatible OPP according to arch/arm/boot/dts/am33xx.dtsi is "opp50-300000000":

    cpu0_opp_table: opp-table {
        compatible = "operating-points-v2-ti-cpu";
        syscon = <&scm_conf>;

        /*
         * The three following nodes are marked with opp-suspend
         * because the can not be enabled simultaneously on a
         * single SoC.
         */
        opp50-300000000 {
            opp-hz = /bits/ 64 <300000000>;
            opp-microvolt = <950000 931000 969000>;
            opp-supported-hw = <0x06 0x0010>;
            opp-suspend;
        };

        opp100-275000000 {
            opp-hz = /bits/ 64 <275000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x01 0x00FF>;
            opp-suspend;
        };

        opp100-300000000 {
            opp-hz = /bits/ 64 <300000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x06 0x0020>;
            opp-suspend;
        };

        opp100-500000000 {
            opp-hz = /bits/ 64 <500000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x01 0xFFFF>;
        };

        opp100-600000000 {
            opp-hz = /bits/ 64 <600000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x06 0x0040>;
        };

        opp120-600000000 {
            opp-hz = /bits/ 64 <600000000>;
            opp-microvolt = <1200000 1176000 1224000>;
            opp-supported-hw = <0x01 0xFFFF>;
        };
[...]

Question 3: Shouldn't "opp100-300000000" be also a compatible mode?

Disabling the cpufreq driver in Linux speeds up the Linux boot process considerably compared to operation at "opp50-300000000". We assume that the MPU PLL settings from U-Boot are left unchanged in this case.

Question 4: Why does it make a difference whether the Linux cpufreq driver is enabled or not if U-Boot configures the MPU PLL correctly to 300MHz?

  • Hi Christoph,
    Thanks for your detailed description of your questions.
    On AM335x, SPL/u-boot sets the max speed supported by the device based on reading CM EFUSE_SMA register @44E107Fc.
    On my AM335x GP EVM, the device is 1GHz part as shown below, and u-boot configures
    get_dpll_mpu_params() based on freq=am335x_get_efuse_mpu_max_freq(cdev), where freq = 0x3E8 (1000) for 1GHz part.

    devmem2 0x44e107fc
    /dev/mem opened.
    Memory mapped at address 0xb6efe000.
    Read at address  0x44E107FC (0xb6efe7fc): 0x00013C2F

    When Dynamic Voltage and Frequency Scaling (DVFS) is enabled, Linux kernel dynamically scale the voltage and frequency based on need,
    user preference, or other factors. Please refer the following link for details on DVFS framework.
    software-dl.ti.com/.../Power_Management.html
    I captured some log for DVFS on AM335x GP EVM with 1GHz part.

    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available__frequencies
    300000 600000 720000 800000 1000000
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
    600000
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
    600000
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available__governors
    conservative userspace powersave ondemand performance
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver
    cpufreq-dt
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table
       From  :    To
             :    300000    600000    720000    800000   1000000
       300000:         0       129        14        15        59
       600000:       126         0         9         7        44
       720000:        20         7         0         4        21
       800000:        22         9         2         0        29
      1000000:        49        42        27        36         0
    root@am335x-hs-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_statte
    300000 79303
    600000 610
    720000 131
    800000 186
    1000000 3556

    Best,

    -Hong

  • Hi Hong,

    thank you for your quick answer. We understand the concept of DVFS but in our case only opp50@300000000 is available. One of our questions is why only this operating point and not at least opp100@300000000 is available.

    Our main question, however, is where exactly the CPU frequency is generated: before or after the "M2" divider? We are still interested in the other questions of course.

    Best regards,
    Christoph

  • Hi Christoph,
    I calculated MPU speed (MHz) vs OPP, and added as the very first column below.

    	{	/* 25 MHz */
    300		{24, 0, 2, -1, -1, -1, -1},	/* OPP 50 */
    		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
    600		{24, 0, 1, -1, -1, -1, -1},	/* OPP 100 */
    720		{144, 4, 1, -1, -1, -1, -1},	/* OPP 120 */
    800		{32, 0, 1, -1, -1, -1, -1},	/* OPP TB */
    1000	{40, 0, 1, -1, -1, -1, -1}	/* OPP NT */
    	},	

    MPU speed is calculated via [M/(N+1)]*CLKINP*[1/M2], where CLKINP=25MHz based on your board setup.
    => 300MHz/OPP50 is configured in SPL/u-boot.
    The formula is in Table 8-17. Output Clocks in Locked Condition of the AM335x TRM.

    For your specific part (300-MHz speed grade), as shown in the AM335x data sheet.
    Table 5-7. VDD_MPU OPPs for ZCZ Package With Device Revision Code "A" or Newer

    OPP100(3) 	1.056 V 1.100 V 1.144 V 300 MHz
    OPP50 		0.912 V 0.950 V 0.988 V 300 MHz
    (3) Applies to all orderable AM335__ZCZ_30 (300-MHz speed grade) devices.

    It looks like OPP100/300MHz and OPP50/300MHz are valid combinations for 300-MHz speed grade.
    But there's also implication with VDD_CORE (for DDR, L3/L4...) as listed in
    Table 5-9. VDD_CORE OPPs for ZCE Package With Device Revision Code "A" or Newer.

    After kernel up, have you checked MPU speed, OPP etc... via omapconf

    ./omapconf show dpll
    ./omapconf show opp

    Best,

    -Hong

  • Hi Hong,

    do you mean to say that MPU speed *is* the CPU speed? In this case am33xx.dtsi should read:

    cpu@0 {
    [...]
    	operating-points-v2 = <&cpu0_opp_table>;
    
    	clocks = <&dpll_mpu_m2_ck>;
    	clock-names = "cpu";
    [...]
    };

    and not

    cpu@0 {
    [...]
    	operating-points-v2 = <&cpu0_opp_table>;
    
    	clocks = <&dpll_mpu_ck>;
    	clock-names = "cpu";
    [...]
    };

    We are most confused by the fact that Linux thinks that the CPU is running at 600MHz while it seems that U-Boot configures it to 300MHz.

    Best regards,
    Christoph

  • Hi Christoph,
    I've run a test with SDK6.3 on AM335x GP EVM with a 1GHz sample.
    I'm attaching the log file when running below cmds which shows ARM MPU speed, OPP, etc... for your reference.
    ARM MPU runs at 600MHz due to DVFS when the log was captured.

    ./omapconf show dpll;
    ./omapconf show opp;
    ./omapconf show pwst;
    cat /proc/cpuinfo;
    cat /sys/kernel/debug/clk/clk_summary

    Best,

    -Hong

    am3_gp_6.3_dvfs.txt
    root@am335x-evm:/usr/bin# ./omapconf show dpll;
    OMAPCONF (rev v1.74-1-g40ab0a2 built Sun Apr 19 07:10:00 UTC 2020)
    
    HW Platform:
      Generic AM33XX (Flattened Device Tree)
      AM3358 ES2.1 GP Device (UNKNOWN performance ZCZ package (1.0GHz))
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
      UNKNOWN POWER IC
    Error: I2C Read failed
      UNKNOWN AUDIO IC
    
    SW Build Details:
      Build:
        Version:  _____                    _____           _         _   
      Kernel:
        Version: 4.19.94-gbe5389fd85
        Author: oe-user@oe-host
        Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
        Type: #1 PREEMPT
        Date: Sun Apr 19 03:43:09 UTC 2020
    
    |--------------------------------------------|
    | DPLL Configuration         | DPLL_PER      |
    |--------------------------------------------|
    | Status                     | Locked        |
    |                            |               |
    | Mode                       | Lock          |
    | Automatic Control          | Not Supported |
    |  LPST = Low-Power STop     |               |
    |  LPBP = Low-Power ByPass   |               |
    |  FRBP = Fast-Relock ByPass |               |
    |  MNBP = MN ByPass          |               |
    |                            |               |
    | Sigma-Delta Divider        | 4             |
    | SELFREQDCO                 | 0             |
    |                            |               |
    | Ref. Frequency (MHz)       | 24.000        |
    | M Multiplier Factor        | 400           |
    | N Divider Factor           | 9             |
    | Lock Frequency (MHz)       | 960           |
    |                            |               |
    | CLKOUT Output              |               |
    |   Status                   | Enabled       |
    |   Clock Divider            | 5             |
    |   Clock Speed (MHz)        | 192           |
    |                            |               |
    | CLK_DCO_LDO Output         |               |
    |   Status                   | Enabled       |
    |   Clock Speed (MHz)        | 960           |
    |                            |               |
    |--------------------------------------------|
    
    |---------------------------------------------------------------------------------------------|
    | DPLL Configuration          | DPLL_CORE     | DPLL_MPU      | DPLL_DDR      | DPLL_DISP     |
    |---------------------------------------------------------------------------------------------|
    | Status                      | Locked        | Locked        | Locked        | Locked        |
    |                             |               |               |               |               |
    | Mode                        | Lock          | Lock          | Lock          | Lock          |
    | Automatic Control           | Not Supported | Not Supported | Not Supported | Not Supported |
    |  LPBP = Low-Power ByPass    |               |               |               |               |
    |  FRBP = Fast-Relock ByPass  |               |               |               |               |
    |  MNBP = MN ByPass           |               |               |               |               |
    | Low-Power Mode              | Disabled      | Disabled      | Disabled      | Disabled      |
    |                             |               |               |               |               |
    | Automatic Recalibration     | Disabled      | Disabled      | Disabled      | Disabled      |
    | Clock Ramping during Relock | Disabled      | Disabled      | Disabled      | Disabled      |
    | Ramping Rate (x REFCLK(s))  | 2             | 2             | 2             | 2             |
    | Ramping Levels              | No Ramp       | No Ramp       | No Ramp       | No Ramp       |
    |                             |               |               |               |               |
    | Bypass Clock                | CLKINP        | CLKINP        | CLKINP        | CLKINP        |
    | Bypass Clock Divider        |               |               |               |               |
    | REGM4XEN Mode               | Disabled      | Disabled      | Disabled      | Disabled      |
    |                             |               |               |               |               |
    | Ref. Frequency (MHz)        | 24.000        | 24.000        | 24.000        | 24.000        |
    | M Multiplier Factor         | 125           | 25            | 101           | 5             |
    | N Divider Factor            | 2             | 0             | 3             | 1             |
    | Lock Frequency (MHz)        | 1000          | 600           | 606           | 60            |
    |                             |               |               |               |               |
    | M2 Output                   |               |               |               |               |
    |   Status                    |               | Enabled       | Enabled       | Enabled       |
    |   Clock Divider             |               | 1             | 2             | 1             |
    |   Clock Speed (MHz)         |               | 600           | 303           | 60            |
    |                             |               |               |               |               |
    | CLK_DCO_LDO Output          |               |               |               |               |
    |   Status                    | Gated         |               |               |               |
    |   Clock Speed (MHz)         | 2000          |               |               |               |
    |                             |               |               |               |               |
    |                             |               |               |               |               |
    | M4 Output                   |               |               |               |               |
    |   Status                    | Enabled       |               |               |               |
    |   Clock Divider             | 10            |               |               |               |
    |   Clock Speed (MHz)         | 200           |               |               |               |
    |                             |               |               |               |               |
    | M5 Output                   |               |               |               |               |
    |   Status                    | Enabled       |               |               |               |
    |   Clock Divider             | 8             |               |               |               |
    |   Clock Speed (MHz)         | 250           |               |               |               |
    |                             |               |               |               |               |
    | M6 Output                   |               |               |               |               |
    |   Status                    | Gated         |               |               |               |
    |   Clock Divider             | 4             |               |               |               |
    |   Clock Speed (MHz)         | 500           |               |               |               |
    |---------------------------------------------------------------------------------------------|
    
    root@am335x-evm:/usr/bin# ./omapconf show opp;
    OMAPCONF (rev v1.74-1-g40ab0a2 built Sun Apr 19 07:10:00 UTC 2020)
    
    HW Platform:
      Generic AM33XX (Flattened Device Tree)
      AM3358 ES2.1 GP Device (UNKNOWN performance ZCZ package (1.0GHz))
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
      UNKNOWN POWER IC
    Error: I2C Read failed
      UNKNOWN AUDIO IC
    
    SW Build Details:
      Build:
        Version:  _____                    _____           _         _   
      Kernel:
        Version: 4.19.94-gbe5389fd85
        Author: oe-user@oe-host
        Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
        Type: #1 PREEMPT
        Date: Sun Apr 19 03:43:09 UTC 2020
    
    omapconf: temp_sensor_voltdm2sensor(): cpu not supported!!!
    omapconf: temp_sensor_voltdm2sensor(): cpu not supported!!!
    cpu_is_online(0): error opening /sys/devices/system/cpu/cpu0/online file!
    |----------------------------------------------------------------------------|
    |                      | Temperature | Voltage | Frequency | OPerating Point |
    |----------------------------------------------------------------------------|
    | VDD_CORE / VDD_CORE0 | NA          | NA      |           | OPP100          |
    |   L3_SLOW            |             |         |  100  MHz |                 |
    |   L3_FAST            |             |         |  200  MHz |                 |
    |   EMIF4              |             |         |  151  MHz |                 |
    |     DDR2/DDR3/mDDR   |             |         |  303  MHz |                 |
    |   L4_PER             |             |         |  100  MHz |                 |
    |   L4_FAST            |             |         |  200  MHz |                 |
    |                      |             |         |           |                 |
    | VDD_MPU / VDD_CORE1  | NA          | NA      |           | OPP100_HIGH     |
    |   MPU (CPU0 OFF)     |             |         |  600  MHz |                 |
    |                      |             |         |           |                 |
    |----------------------------------------------------------------------------|
    
    Notes:
      (1) Module is disabled, rate may not be relevant.
    
    root@am335x-evm:/usr/bin# ./omapconf show pwst;
    OMAPCONF (rev v1.74-1-g40ab0a2 built Sun Apr 19 07:10:00 UTC 2020)
    
    HW Platform:
      Generic AM33XX (Flattened Device Tree)
      AM3358 ES2.1 GP Device (UNKNOWN performance ZCZ package (1.0GHz))
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
      UNKNOWN POWER IC
    Error: I2C Read failed
      UNKNOWN AUDIO IC
    
    SW Build Details:
      Build:
        Version:  _____                    _____           _         _   
      Kernel:
        Version: 4.19.94-gbe5389fd85
        Author: oe-user@oe-host
        Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
        Type: #1 PREEMPT
        Date: Sun Apr 19 03:43:09 UTC 2020
    
    |---------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | OMAP Power Status                                                                                                                                            |
    |---------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | Voltage Domain                | Power Domain                 | Clock Domain          | Module Status                                                          |
    | Name              | OPP       | Name       | Curr.  | Target | Name       | Status   | Name                  | Rate (MHz) | Idle                 | Standby    |
    |---------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | VDD_CORE          | OPP100    | WKUP       | OFF    | OFF    | L4WKUP     | Running  | L4_WKUP_INTERCONNECT  | 100.000    | Full ON              |            |
    |                   |           |            |        |        |------------------------------------------------------------------------------------------------|
    |                   |           |            |        |        | WKUP_L3_AON | Running  | DEBUGSS               | 200.000    | In Transition        | Functional |
    |                   |           |-------------------------------------------------------------------------------------------------------------------------------|
    |                   |           | GFX        | ON     | ON     | GFX_L3     | Running  | GFX                   | 100.000    | Full ON              | Functional |
    |                   |           |-------------------------------------------------------------------------------------------------------------------------------|
    |                   |           | PER        | ON     | ON     | L4_SLOW    | Running  | L4_PER_INTERCONNECT   | 100.000    | Full ON              |            |
    |                   |           |            |        |        |------------------------------------------------------------------------------------------------|
    |                   |           |            |        |        | L3_SLOW    | Running  | L3_MAIN1_INTERCONNECT | 100.000    | Full ON              |            |
    |                   |           |            |        |        |------------------------------------------------------------------------------------------------|
    |                   |           |            |        |        | L3_FAST    | Running  | L3_MAIN2_INTERCONNECT | 200.000    | Full ON              |            |
    |                   |           |            |        |        |            |          | EMIF4                 | 151.500    | Full ON              |            |
    |                   |           |            |        |        |            |          | PHY_EMIF              | 303.000    |                      |            |
    |                   |           |            |        |        |------------------------------------------------------------------------------------------------|
    |                   |           |            |        |        | L4_FAST    | Running  | L4_FAST_INTERCONNECT  | 200.000    | Full ON              |            |
    |---------------------------------------------------------------------------------------------------------------------------------------------------------------|
    | VDD_MPU           | OPP_TURBO | MPU        | ON     | ON     | MPU        | Running  | MPU                   | 800.000    | Full ON              |            |
    |---------------------------------------------------------------------------------------------------------------------------------------------------------------|
    root@am335x-evm:/usr/bin# cat /proc/cpuinfo;
    processor	: 0
    model name	: ARMv7 Processor rev 2 (v7l)
    BogoMIPS	: 298.84
    Features	: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 
    CPU implementer	: 0x41
    CPU architecture: 7
    CPU variant	: 0x3
    CPU part	: 0xc08
    CPU revision	: 2
    
    Hardware	: Generic AM33XX (Flattened Device Tree)
    Revision	: 0000
    Serial		: 05154P160003
    root@am335x-evm:/usr/bin# cat /sys/kernel/debug/clk/clk_summary
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     tclkin_ck                            0        0        0    12000000          0     0  50000
     virt_26000000_ck                     0        0        0    26000000          0     0  50000
     virt_25000000_ck                     0        0        0    25000000          0     0  50000
     virt_24000000_ck                     1        1        0    24000000          0     0  50000
        sys_clkin_ck                     11       23        0    24000000          0     0  50000
           timer6_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:00dc:0        0        1        0    24000000          0     0  50000
           timer3_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:0070:0        0        1        0    24000000          0     0  50000
           timer7_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:0068:0        0        1        0    24000000          0     0  50000
           timer5_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:00d8:0        0        1        0    24000000          0     0  50000
           timer4_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:0074:0        0        1        0    24000000          0     0  50000
           timer2_fck                     1        1        0    24000000          0     0  50000
              l4_per_cm:clk:006c:0        1        1        0    24000000          0     0  50000
           timer1_fck                     1        1        0    24000000          0     0  50000
              l4_wkup_cm:clk:00c0:0       1        1        0    24000000          0     0  50000
           dpll_per_ck                    1        2        0   960000000          0     0  50000
              usbotg_fck                  0        1        0   960000000          0     0  50000
                 l4_per_cm:clk:0008:0       0        1        0   960000000          0     0  50000
              dpll_per_m2_ck              3        4        0   192000000          0     0  50000
                 mmc_clk                  0        3        0    96000000          0     0  50000
                    l4_per_cm:clk:0028:0       0        1        0    96000000          0     0  50000
                    l4_per_cm:clk:00e0:0       0        1        0    96000000          0     0  50000
                    l4_per_cm:clk:00e4:0       0        1        0    96000000          0     0  50000
                 clk_24mhz                1        1        0    24000000          0     0  50000
                    clkdiv32k_ck          1        1        0       32786          0     0  50000
                       l4_per_cm:clk:0138:0       1        5        0       32786          0     0  50000
                          wdt1_fck        0        1        0       32786          0     0  50000
                             l4_wkup_cm:clk:00d0:0       0        1        0       32786          0     0  50000
                          l4_per_cm:clk:0098:18       0        2        0       32786          0     0  50000
                          l4_per_cm:clk:009c:18       0        2        0       32786          0     0  50000
                          l4_per_cm:clk:00a0:18       0        2        0       32786          0     0  50000
                 dpll_per_m2_div4_ck       1        9        0    48000000          0     0  50000
                    l4_per_cm:clk:0024:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0030:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0034:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0038:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:003c:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0058:0       1        1        0    48000000          0     0  50000
                    l4_per_cm:clk:005c:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0060:0       0        1        0    48000000          0     0  50000
                    l4_per_cm:clk:0064:0       0        1        0    48000000          0     0  50000
                 dpll_per_m2_div4_wkupdm_ck       2        2        0    48000000          0     0  50000
                    l4_wkup_cm:clk:00b0:0       1        1        0    48000000          0     0  50000
                    l4_wkup_cm:clk:00b4:0       1        1        0    48000000          0     0  50000
           dpll_disp_ck                   1        1        0    60000000          0     0  50000
              dpll_disp_m2_ck             1        1        0    60000000          0     0  50000
                 lcd_gclk                 1        1        0    60000000          0     0  50000
                    l4_per_cm:clk:0004:0       1        1        0    60000000          0     0  50000
           dpll_ddr_ck                    1        1        0   606000000          0     0  50000
              dpll_ddr_m2_ck              2        2        0   303000000          0     0  50000
                 dpll_ddr_m2_div2_ck       1        1        0   151500000          0     0  50000
                    l4_per_cm:clk:0014:0       1        1        0   151500000          0     0  50000
           dpll_mpu_ck                    1        1        0   600000000          0     0  50000
              dpll_mpu_m2_ck              4        4        0   600000000          0     0  50000
                 mpu_cm:clk:0000:0        1        1        0   600000000          0     0  50000
           dpll_core_ck                   1        1        0  1000000000          0     0  50000
              dpll_core_x2_ck             2        2        0  2000000000          0     0  50000
                 dpll_core_m6_ck          0        0        0   500000000          0     0  50000
                 dpll_core_m5_ck          2        2        0   250000000          0     0  50000
                    cpsw_cpts_rft_clk       1        1        0   250000000          0     0  50000
                    cpsw_125mhz_gclk       2        3        0   125000000          0     0  50000
                       l4_per_cm:clk:0000:0       1        1        0   125000000          0     0  50000
                 dpll_core_m4_ck         10       11        0   200000000          0     0  50000
                    gfx_fclk_clksel_ck       1        1        0   200000000          0     0  50000
                       gfx_fck_div_ck       1        1        0   200000000          0     0  50000
                          gfx_l3_cm:clk:0000:0       1        1        0   200000000          0     0  50000
                    sysclk_div_ck         0        0        0   200000000          0     0  50000
                    l4hs_gclk             2        2        0   200000000          0     0  50000
                       l4_per_cm:clk:010c:0       1        1        0   200000000          0     0  50000
                    l4_rtc_gclk           0        0        0   100000000          0     0  50000
                    dpll_core_m4_div2_ck      17       18        0   100000000          0     0  50000
                       l4ls_gclk         37       41        0   100000000          0     0  50000
                          ehrpwm2_tbclk       0        0        0   100000000          0     0  50000
                          ehrpwm1_tbclk       0        0        0   100000000          0     0  50000
                          ehrpwm0_tbclk       0        0        0   100000000          0     0  50000
                          l4_per_cm:clk:002c:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:004c:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:0098:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:009c:0       0        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00a0:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00b8:0       0        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00c0:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00c4:0       0        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00f8:0       0        1        0   100000000          0     0  50000
                          l4_per_cm:clk:00fc:0       1        1        0   100000000          0     0  50000
                          l4_per_cm:clk:011c:0       0        0        0   100000000          0     0  50000
                       l4fw_gclk          1        1        0   100000000          0     0  50000
                       l3s_gclk           9       10        0   100000000          0     0  50000
                          l4_per_cm:clk:001c:0       1        1        0   100000000          0     0  50000
                       ieee5000_fck       0        0        0   100000000          0     0  50000
                       l4_wkup_cm:clk:0000:0       1        1        0   100000000          0     0  50000
                       l4_wkup_cm:clk:0004:0       1        1        0   100000000          0     0  50000
                       l4_wkup_cm:clk:0008:0       1        1        0   100000000          0     0  50000
                       l4_wkup_cm:clk:00ac:0       0        1        0   100000000          0     0  50000
                    mmu_fck               0        0        0   200000000          0     0  50000
                    l3_gclk              14       15        0   200000000          0     0  50000
                       pruss_ocp_gclk       1        1        0   200000000          0     0  50000
                          l4_per_cm:clk:00d4:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:0010:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:0018:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:008c:0       0        1        0   200000000          0     0  50000
                       l4_per_cm:clk:00a8:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:00c8:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:00cc:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:00e8:0       1        1        0   200000000          0     0  50000
                       l4_per_cm:clk:00ec:0       1        1        0   200000000          0     0  50000
                    l4_wkup_cm:clk:0010:30       0        2        0   200000000          0     0  50000
                       l4_wkup_cm:clk:0010:20       0        1        0   200000000          0     0  50000
                          l4_wkup_cm:clk:0010:24       0        1        0    50000000          0     0  50000
                             l4_wkup_cm:clk:0010:0       0        1        0    50000000          0     0  50000
                       l4_wkup_cm:clk:0010:22       0        0        0   200000000          0     0  50000
                          l4_wkup_cm:clk:0010:27       0        0        0    50000000          0     0  50000
           rng_fck                        2        2        0    24000000          0     0  50000
              l4_per_cm:clk:007c:0        1        1        0    24000000          0     0  50000
           aes0_fck                       1        2        0    24000000          0     0  50000
              l4_per_cm:clk:0080:0        0        1        0    24000000          0     0  50000
           sha0_fck                       1        1        0    24000000          0     0  50000
           smartreflex1_fck               0        1        0    24000000          0     0  50000
              l4_wkup_cm:clk:00c4:0       0        1        0    24000000          0     0  50000
           smartreflex0_fck               0        1        0    24000000          0     0  50000
              l4_wkup_cm:clk:00bc:0       0        1        0    24000000          0     0  50000
           mcasp1_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:0054:0        0        1        0    24000000          0     0  50000
           mcasp0_fck                     0        1        0    24000000          0     0  50000
              l4_per_cm:clk:0020:0        0        1        0    24000000          0     0  50000
           dcan1_fck                      0        1        0    24000000          0     0  50000
              l4_per_cm:clk:00b0:0        0        1        0    24000000          0     0  50000
           dcan0_fck                      0        1        0    24000000          0     0  50000
              l4_per_cm:clk:00ac:0        0        1        0    24000000          0     0  50000
           adc_tsc_fck                    1        1        0    24000000          0     0  50000
              l4_wkup_cm:clk:00b8:0       1        1        0    24000000          0     0  50000
           l4_wkup_cm:clk:0010:19         0        1        0    24000000          0     0  50000
           l4_cefuse_cm:clk:0000:0        0        0        0    24000000          0     0  50000
     virt_19200000_ck                     0        0        0    19200000          0     0  50000
     clk_rc32k_ck                         1        1        0       32000          0     0  50000
        gpio0_dbclk_mux_ck                1        1        0       32000          0     0  50000
           l4_wkup_cm:clk:0004:18         1        2        0       32000          0     0  50000
     clk_32768_ck                         3        3        0       32768          0     0  50000
        sysclkout_pre_ck                  1        1        0       32768          0     0  50000
           clkout2_div_ck                 1        1        0       32768          0     0  50000
              clkout2_ck                  1        1        0       32768          0     0  50000
        l4_rtc_cm:clk:0000:0              1        1        0       32768          0     0  50000
    root@am335x-evm:/usr/bin# 
    root@am335x-evm:/usr/bin# 

  • Hi Hong,

    thank you. But I have to insist:

    1. Do you mean to say that MPU speed *is* the CPU speed?
    2. Where exactly is the CPU frequency generated: before or after the "M2" divider?

    And what about the device tree?

    Best regards,
    Christoph

  • Hi Christoph,
    AM335x Power, Reset, and Clock Management (PRCM) (AM335x TRM Chatper 8) is responsible to generating clocks
    for MPU (ARM cortex-A8), core, display, DDR, peripherals.
    For example, in Figure 8-1 (AM335x Device Nomenclature) of AM335x Data Sheet,
    30 = 300-MHz Cortex-A8 => 300MHZ is the max speed of MPU or ARM Cortex-A8 core is able to run.

    For your questions
    1. Do you mean to say that MPU speed *is* the CPU speed?
    Yes,
    2. Where exactly is the CPU frequency generated: before or after the "M2" divider?
    MPU clock is generated as shown in Figure 8-8. ADPLLS of AM335x TRM, or after "M2" divider.

    And what about the device tree?
    Have you tried running cmds in my last reply for showing MPU speed, OPP etc...under DVFS, and see any correlation with your device tree setup?

    Best,

    -Hong

  • Hi Hong,

    thank you for confirmation! Yes, I have run those commands: They definitely erroneously report a CPU rate of 600MHz when U-Boot sets M2 divider to 2 for 300MHz (25MHz oscillator * 24 / 2 (= M2)). So am33xx.dtsi should read:

    / {
    	cpus {
    		cpu@0 {
    			clocks = <&dpll_mpu_m2_ck>;
    		};
    	};
    };

    Best regards,
    Christoph