This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6548: CPSW (RMII) + DP83822

Part Number: AM6548
Other Parts Discussed in Thread: DRA829

Hi TI Team,

Does the latest Linux sdk support to config CPSW with RMII mode?

We use CPSW with RMII interface to DP83822 PHY on our custom board.

The SDK I use is ti-processor-sdk-linux-rt-am65xx-evm-07_00_01_07.

The Link Up/Down state is working well.

But I can't ping to PC successfully....

The dts as below

mcu_cpsw_pins_default: mcu_cpsw_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 1) /* (N4) MCU_RGMII1_TX_CTL.MCU_RMII1_CRS_DV */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 1) /* (N5) MCU_RGMII1_RX_CTL.MCU_RMII1_RX_ER */
AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 1) /* (M4) MCU_RGMII1_TD1.MCU_RMII1_TXD1 */
AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 1) /* (M5) MCU_RGMII1_TD0.MCU_RMII1_TXD0 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 1) /* (M6) MCU_RGMII1_RD1.MCU_RMII1_RXD1 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 1) /* (L6) MCU_RGMII1_RD0.MCU_RMII1_RXD0 */
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 1) /* (N1) MCU_RGMII1_TXC.MCU_RMII1_TX_EN */
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 1) /* (M1) MCU_RGMII1_RXC.MCU_RMII1_REF_CLK */
>;

};

mcu_mdio_pins_default: mcu_mdio1_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};

&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

cpts {
ti,pps = <3 1>;
};
};

&davinci_mdio {
reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_LOW
&main_gpio1 17 GPIO_ACTIVE_LOW
>;
reset-delay-us = <20>; /* PHY datasheet states 1uS min */

phy0: ethernet-phy@0 {
reg = <1>;
};
};

&cpsw_port1 {
phy-mode = "rmii";
phy-handle = <&phy0>;
};

#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x80000000 | val)

&timesync_router {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpts>;

/* Example of the timesync routing */
mcu_cpts: mcu_cpts {
pinctrl-single,pins = <
/* pps [cpts genf1] in13 -> out25 [cpts hw4_push] */
TS_OFFSET(25, 13)
>;
};
};

Any suggestion?

Thanks

  • Hi,

    I find a related discuss.

    Based on it, I set CPSW_PN_MAC_CONTROL_REG(0x46022330) to 0x8021 and our board can ping success now.

    However, I have a problem about setting RMII_CLK_SEL bit in CTRLMMR_MCU_ENET_CLKSEL register.

    Our rmii clock source is from MCU_RMII_REFCLK pin.

    So, I try to set CTRLMMR_MCU_ENET_CLKSEL register to 1.

    But, the register value always be restore to 0.

    How to change CTRLMMR_MCU_ENET_CLKSEL register value?

    Thanks

  • Joey,

    Can you read the MMR at 0x40F05008 and confirm the value when you are trying to write to 0x40f08050?

    Best regards,

    Dave

  • Hi Dave,

    The value of 0x40F05008 is 0x68EF3491.

    Thanks

  • Joey,

    Thanks and apologies for the delay. I was without my platform but have it back now. I was suspecting at first that the MMRs were locked, and this last check was to confirm the lock status. It is, however, unlocked (UNLOCKED status is bit 0). I've since reproduced the same on my setup and see that I also cannot update this register with the devmem2 command, which is strange, and I do see this is working on the DRA829 with the same command. I'm following up to see what may be blocking and will update soon.

    Best regards,

    Dave

  • Joey,

    My apologies, but I pointed you to the incorrect lock register. The CTRLMMR_MCU_ENET_CLKSEL(0x40f0_8050) register belongs to partition 2 and we checked partition 1. Please check CTRLMMR_MCU_LOCK (0x40f0_9008).

    Likely this will read 0x0, meaning the CTRLMMR space for the clock select cannot be modified.

    You can unlock the region prior to updating by writing to the lock register pair at 0x40f0_9008 and _900c. Refer to the TRM section 5.1.2.3.1.1 for instructions, but you write the lock values to each and then 40f0_9008 bit 0 will reflect the region is unlocked:

    root@am65xx-evm:~# devmem2 0x40f09008 w
    /dev/mem opened.
    Memory mapped at address 0xffff9e620000.
    Read at address 0x40F09008 (0xffff9e629008): 0x00000000
    root@am65xx-evm:~# devmem2 0x40f09008 w 0x68ef3490
    /dev/mem opened.
    Memory mapped at address 0xffff8a6a0000.
    Read at address 0x40F09008 (0xffff8a6a9008): 0x00000000
    Write at address 0x40F09008 (0xffff8a6a9008): 0x68EF3490, readback 0x68EF3490
    root@am65xx-evm:~# devmem2 0x40f0900c w 0xd172bc5a
    /dev/mem opened.
    Memory mapped at address 0xffffaf4d0000.
    Read at address 0x40F0900C (0xffffaf4d900c): 0x00000000
    Write at address 0x40F0900C (0xffffaf4d900c): 0xD172BC5A, readback 0xD172BC5A
    root@am65xx-evm:~# devmem2 0x40f09008
    /dev/mem opened.
    Memory mapped at address 0xffff88640000.
    Read at address 0x40F09008 (0xffff88649008): 0x68EF3491
    root@am65xx-evm:~# devmem2 0x40f08050
    /dev/mem opened.
    Memory mapped at address 0xffffadeb0000.
    Read at address 0x40F08050 (0xffffadeb8050): 0x00000000
    root@am65xx-evm:~# devmem2 0x40f08050 w 1
    /dev/mem opened.
    Memory mapped at address 0xffff86610000.
    Read at address 0x40F08050 (0xffff86618050): 0x00000000
    Write at address 0x40F08050 (0xffff86618050): 0x00000001, readback 0x00000001
    root@am65xx-evm:~# devmem2 0x40f08050
    /dev/mem opened.
    Memory mapped at address 0xffffbc2d0000.
    Read at address 0x40F08050 (0xffffbc2d8050): 0x00000001

    Best regards,

    Dave