TDA2EG-17: DDR - 30 ℃ test abnormal

gg yang

Expert 1310 points

Part Number: TDA2EG-17
Other Parts Discussed in Thread: DRA71

Hi，

The micro DDR memtester was tested at room temperature for 12 hours without any abnormality.

In the low temperature - 30 ℃ test, there is abnormal, what is the possible reason?

The configuration parameters of DDR have been used on tda2ex, and the low temperature test is normal.

over 5 years ago

0 Kevin S over 5 years ago

TI__Mastermind 41780 points

Hi,

How many units have been tested, and how many units show this behavior?

Can you give more information regarding the failure? (ex: log file)?

Thanks,
Kevin

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

SDK： ti-processor-sdk-linux-automotive-dra7xx-evm-03_04_00_03

uboot：

VERSION = 2016
PATCHLEVEL = 05

In the DDR configuration file avatar_ EMIF_ RegisterConfigt.xlsm If the "leveling technique:" s / W "in" is set to HW, why can't there be any output and start? If it is set to SW, uboot can start normally.

I have compared the differences between HW and SW in the following aspects:

Sw:

.emif_ Rd_ Wr_ lvl_ rmp_ ctl = 0x00000000,

.emif_ ddr_ phy_ ctlr_ 1_ init = 0x0E24400F,

Hw:

.emif_ Rd_ Wr_ lvl_ rmp_ ctl = 0x80000000,

.emif_ ddr_ phy_ ctlr_ 1_ init = 0x0824400F,

Is tda2eg-17 supported HW ？

If the configuration is hw, it can not be started at normal temperature.

When the configuration is SW, it can start at low temperature, but there is abnormality,

Log of two boards ，The configuration is SW, but the test is abnormal at low temperature：

Fullscreen 1_board.log Download

[15:03:06]Usage: ./memtester [-p physaddrbase] <mem>[B|K|M|G] [loops]
[15:03:14]root@dra7xx-evm:/datafs# ./memtester 500M 10
[15:03:14]memtester version 4.1.3 (32-bit)
[15:03:14]Copyright (C) 2010 Charles Cazabon.
[15:03:14]Licensed under the GNU General Public License version 2 (only).
[15:03:14]
[15:03:14]pagesize is 4096
[15:03:14]pagesizemask is 0xfffff000
[15:03:14]want 500MB (524288000 bytes)
[15:03:14]got  500MB (524288000 bytes), trying mlock ...locked.
[15:03:14]Loop 1/10:
[15:03:44]  Stuck Address       : ok         
[15:04:07]  Random Value        : ok
[15:04:07]  Compare XOR         : ok
[15:04:08]  Compare SUB         : ok
[15:04:09]  Compare MUL         : ok
[15:04:11]  Compare DIV         : ok
[15:04:12]  Compare OR          : ok
[15:04:13]  Compare AND         : ok
[15:04:13]  Sequential Increment: ok
[15:05:06]  Solid Bits          : ok         
[15:08:36]  Block Sequential    : ok         
[15:09:28]  Checkerboard        : ok         
[15:10:21]  Bit Spread          : ok         
[15:13:51]  Bit Flip            : ok         
[15:14:43]  Walking Ones        : ok         
[15:15:36]  Walking Zeroes      : ok         
[15:15:36]
[15:15:36]Loop 2/10:
[15:16:05]  Stuck Address       : ok         
[15:16:28]  Random Value        : ok
[15:16:29]  Compare XOR         : ok
[15:16:30]  Compare SUB         : ok
[15:16:30]  Compare MUL         : ok
[15:16:32]  Compare DIV         : ok
[15:16:33]  Compare OR          : ok
[15:16:34]  Compare AND         : ok
[15:16:35]  Sequential Increment: ok
[15:17:27]  Solid Bits          : ok         
[15:20:57]  Block Sequential    : ok         
[15:21:50]  Checkerboard        : ok         
[15:22:42]  Bit Spread          : ok         
[15:26:12]  Bit Flip            : ok         
[15:27:05]  Walking Ones        : ok         
[15:27:57]  Walking Zeroes      : ok         
[15:27:57]
[15:27:57]Loop 3/10:
[15:28:27]  Stuck Address       : ok         
[15:28:49]  Random Value        : ok
[15:28:50]  Compare XOR         : ok
[15:28:51]  Compare SUB         : ok
[15:28:52]  Compare MUL         : ok
[15:28:55]  Compare DIV         : ok
[15:28:55]  Compare OR          : ok
[15:28:56]  Compare AND         : ok
[15:28:57]  Sequential Increment: ok
[15:29:50]  Solid Bits          : ok         
[15:33:20]  Block Sequential    : ok         
[15:34:12]  Checkerboard        : ok         
[15:35:04]  Bit Spread          : ok         
[15:38:34]  Bit Flip            : ok         
[15:39:27]  Walking Ones        : ok         
[15:40:19]  Walking Zeroes      : ok         
[15:40:19]
[15:40:19]Loop 4/10:
[15:40:49]  Stuck Address       : ok         
[15:41:12]  Random Value        : ok
[15:41:12]  Compare XOR         : ok
[15:41:13]  Compare SUB         : ok
[15:41:14]  Compare MUL         : ok
[15:41:17]  Compare DIV         : ok
[15:41:18]  Compare OR          : ok
[15:41:19]  Compare AND         : ok
[15:41:19]  Sequential Increment: ok
[15:42:12]  Solid Bits          : ok         
[15:45:42]  Block Sequential    : ok         
[15:46:34]  Checkerboard        : ok         
[15:47:27]  Bit Spread          : ok         
[15:50:57]  Bit Flip            : ok         
[15:51:49]  Walking Ones        : ok         
[15:52:42]  Walking Zeroes      : ok         
[15:52:42]
[15:52:42]Loop 5/10:
[15:53:11]  Stuck Address       : ok         
[15:53:34]  Random Value        : ok
[15:53:35]  Compare XOR         : ok
[15:53:36]  Compare SUB         : ok
[15:53:37]  Compare MUL         : ok
[15:53:39]  Compare DIV         : ok
[15:53:40]  Compare OR          : ok
[15:53:41]  Compare AND         : ok
[15:53:42]  Sequential Increment: ok
[15:54:34]  Solid Bits          : ok         
[15:58:04]  Block Sequential    : ok         
[15:58:57]  Checkerboard        : ok         
[15:59:49]  Bit Spread          : ok         
[16:03:19]  Bit Flip            : ok         
[16:04:12]  Walking Ones        : ok         
[16:05:04]  Walking Zeroes      : ok         
[16:05:04]
[16:05:04]Loop 6/10:
[16:05:34]  Stuck Address       : ok         
[16:05:56]  Random Value        : ok
[16:05:57]  Compare XOR         : ok
[16:05:58]  Compare SUB         : ok
[16:05:59]  Compare MUL         : ok
[16:06:02]  Compare DIV         : ok
[16:06:03]  Compare OR          : ok
[16:06:03]  Compare AND         : ok
[16:06:04]  Sequential Increment: ok
[16:06:57]  Solid Bits          : ok         
[16:10:27]  Block Sequential    : ok         
[16:11:19]  Checkerboard        : ok         
[16:12:12]  Bit Spread          : ok         
[16:15:42]  Bit Flip            : ok         
[16:16:34]  Walking Ones        : ok         
[16:17:27]  Walking Zeroes      : ok         
[16:17:27]
[16:17:27]Loop 7/10:
[16:17:56]  Stuck Address       : ok         
[16:18:19]  Random Value        : ok
[16:18:20]  Compare XOR         : ok
[16:18:20]  Compare SUB         : ok
[16:18:21]  Compare MUL         : ok
[16:18:25]  Compare DIV         : ok
[16:18:26]  Compare OR          : ok
[16:18:27]  Compare AND         : ok
[16:18:27]  Sequential Increment: ok
[16:19:20]  Solid Bits          : ok         
[16:21:56]  Block Sequential    : testing 190
[16:21:56]
[16:21:57]setting 191
[16:22:50]ok         
[16:23:42]  Checkerboard        : ok         
[16:24:35]  Bit Spread          : ok         
[16:28:05]  Bit Flip            : ok         
[16:28:57]  Walking Ones        : ok         
[16:29:50]  Walking Zeroes      : ok         
[16:29:50]
[16:29:50]Loop 8/10:
[16:30:19]  Stuck Address       : ok         
[16:30:42]  Random Value        : ok
[16:30:43]  Compare XOR         : ok
[16:30:44]  Compare SUB         : ok
[16:30:44]  Compare MUL         : ok
[16:30:46]  Compare DIV         : ok
[16:30:47]  Compare OR          : ok
[16:30:47]  Compare AND         : ok
[16:30:48]  Sequential Increment: ok
[16:31:41]  Solid Bits          : ok         
[16:35:11]  Block Sequential    : ok         
[16:36:03]  Checkerboard        : ok         
[16:36:56]  Bit Spread          : ok         
[16:40:26]  Bit Flip            : ok         
[16:41:18]  Walking Ones        : ok         
[16:42:11]  Walking Zeroes      : ok         
[16:42:11]
[16:42:11]Loop 9/10:
[16:42:40]  Stuck Address       : ok         
[16:43:03]  Random Value        : ok
[16:43:04]  Compare XOR         : ok
[16:43:04]  Compare SUB         : ok
[16:43:05]  Compare MUL         : ok
[16:43:07]  Compare DIV         : ok
[16:43:08]  Compare OR          : ok
[16:43:09]  Compare AND         : ok
[16:43:10]  Sequential Increment: ok
[16:44:02]  Solid Bits          : ok         
[16:47:32]  Block Sequential    : ok         
[16:48:25]  Checkerboard        : ok         
[16:49:17]  Bit Spread          : ok         
[16:52:00]  Bit Flip            : testing 197FAILURE: 0xfeffffff != 0xfeff0000 at offset 0x039667ff.
[16:52:00]FAILURE: 0x01000000 != 0x0100ffff at offset 0x03966800.
[16:52:00]FAILURE: 0xfeffffff != 0xfeff0000 at offset 0x03966801.
[16:52:00]FAILURE: 0x01000000 != 0x0100ffff at offset 0x03966802.
[16:52:00]FAILURE: 0xfeffffff != 0xfeff0000 at offset 0x03966803.
[16:52:00]FAILURE: 0x01000000 != 0x0100ffff at offset 0x03966804.
[16:52:00]FAILURE: 0xfeffffff != 0xfeff0000 at offset 0x03966805.
[16:52:00]FAILURE: 0x01000000 != 0x0100ffff at offset 0x03966806.
[16:52:52]  Walking Ones        : ok         
[16:53:45]  Walking Zeroes      : ok

Fullscreen 2_board.log Download

root@dra7xx-evm:/datafs# ./memtester 500M 10
[15:07:50]memtester version 4.1.3 (32-bit)
[15:07:50]Copyright (C) 2010 Charles Cazabon.
[15:07:50]Licensed under the GNU General Public License version 2 (only).
[15:07:50]
[15:07:50]pagesize is 4096
[15:07:50]pagesizemask is 0xfffff000
[15:07:50]want 500MB (524288000 bytes)
[15:07:51]got  500MB (524288000 bytes), trying mlock ...locked.
[15:07:51]Loop 1/10:
[15:08:20]  Stuck Address       : ok         
[15:08:43]  Random Value        : ok
[15:08:44]  Compare XOR         : ok
[15:08:45]  Compare SUB         : ok
[15:08:45]  Compare MUL         : ok
[15:08:47]  Compare DIV         : ok
[15:08:48]  Compare OR          : ok
[15:08:49]  Compare AND         : ok
[15:08:50]  Sequential Increment: ok
[15:08:52]  Solid Bits          : testing   2FAILURE: 0x00000000 != 0x0000ffff at offset 0x0328fa0f.
[15:08:52]FAILURE: 0xffffffff != 0xffff0000 at offset 0x0328fa10.
[15:08:52]FAILURE: 0x00000000 != 0x0000ffff at offset 0x0328fa11.
[15:08:52]FAILURE: 0xffffffff != 0xffff0000 at offset 0x0328fa12.
[15:08:52]FAILURE: 0x00000000 != 0x0000ffff at offset 0x0328fa13.
[15:08:52]FAILURE: 0xffffffff != 0xffff0000 at offset 0x0328fa14.
[15:08:52]FAILURE: 0x00000000 != 0x0000ffff at offset 0x0328fa15.
[15:08:52]FAILURE: 0xffffffff != 0xffff0000 at offset 0x0328fa16.
[15:12:21]  Block Sequential    : ok         
[15:13:14]  Checkerboard        : ok         
[15:14:00]  Bit Spread          : testing  56FAILURE: 0x00000500 != 0x00000280 at offset 0x00d2c010.
[15:14:00]FAILURE: 0xfffffaff != 0xfffffd7f at offset 0x00d2c011.
[15:14:00]FAILURE: 0x00000500 != 0x00000280 at offset 0x00d2c012.
[15:14:00]FAILURE: 0xfffffaff != 0xfffffd7f at offset 0x00d2c013.
[15:14:00]FAILURE: 0x00000500 != 0x00000280 at offset 0x00d2c014.
[15:14:00]FAILURE: 0xfffffaff != 0xfffffd7f at offset 0x00d2c015.
[15:14:00]FAILURE: 0x00000500 != 0x00000280 at offset 0x00d2c016.
[15:14:00]FAILURE: 0xfffffaff != 0xfffffd7f at offset 0x00d2c017.
[15:14:01]  Bit Flip            : testing   0FAILURE: 0xffff0280 != 0xfffffffe at offset 0x0163bc10.
[15:14:01]FAILURE: 0x0000fd7f != 0x00000001 at offset 0x0163bc11.
[15:14:01]FAILURE: 0xffff0280 != 0xfffffffe at offset 0x0163bc12.
[15:14:01]FAILURE: 0x0000fd7f != 0x00000001 at offset 0x0163bc13.
[15:14:01]FAILURE: 0xffff0280 != 0xfffffffe at offset 0x0163bc14.
[15:14:01]FAILURE: 0x0000fd7f != 0x00000001 at offset 0x0163bc15.
[15:14:01]FAILURE: 0xffff0280 != 0xfffffffe at offset 0x0163bc16.
[15:14:01]FAILURE: 0x0000fd7f != 0x00000001 at offset 0x0163bc17.
[15:14:53]  Walking Ones        : ok         
[15:15:46]  Walking Zeroes      : ok         
[15:15:46]
[15:15:46]Loop 2/10:
[15:16:15]  Stuck Address       : ok         
[15:16:38]  Random Value        : ok
[15:16:39]  Compare XOR         : ok
[15:16:39]  Compare SUB         : ok
[15:16:40]  Compare MUL         : ok
[15:16:42]  Compare DIV         : ok
[15:16:43]  Compare OR          : ok
[15:16:44]  Compare AND         : ok
[15:16:45]  Sequential Increment: ok
[15:16:54]  Solid Bits          : testing  11FAILURE: 0x0000ffff != 0x00000000 at offset 0x033e6410.
[15:16:54]FAILURE: 0xffff0000 != 0xffffffff at offset 0x033e6411.
[15:16:54]FAILURE: 0x0000ffff != 0x00000000 at offset 0x033e6412.
[15:16:54]FAILURE: 0xffff0000 != 0xffffffff at offset 0x033e6413.
[15:16:54]FAILURE: 0x0000ffff != 0x00000000 at offset 0x033e6414.
[15:16:54]FAILURE: 0xffff0000 != 0xffffffff at offset 0x033e6415.
[15:16:54]FAILURE: 0x0000ffff != 0x00000000 at offset 0x033e6416.
[15:16:54]FAILURE: 0xffff0000 != 0xffffffff at offset 0x033e6417.
[15:20:24]  Block Sequential    : ok         
[15:21:16]  Checkerboard        : ok         
[15:21:26]  Bit Spread          : testing  11FAILURE: 0xffffd7ff != 0xffffebff at offset 0x0315fb4f.
[15:21:26]FAILURE: 0x00002800 != 0x00001400 at offset 0x0315fb50.
[15:21:26]FAILURE: 0xffffd7ff != 0xffffebff at offset 0x0315fb51.
[15:21:26]FAILURE: 0x00002800 != 0x00001400 at offset 0x0315fb52.
[15:21:26]FAILURE: 0xffffd7ff != 0xffffebff at offset 0x0315fb53.
[15:21:26]FAILURE: 0x00002800 != 0x00001400 at offset 0x0315fb54.
[15:21:26]FAILURE: 0xffffd7ff != 0xffffebff at offset 0x0315fb55.
[15:21:26]FAILURE: 0x00002800 != 0x00001400 at offset 0x0315fb56.
[15:21:57]  Bit Flip            : testing  37FAILURE: 0xffffffef != 0xffff0010 at offset 0x032bce0f.
[15:21:57]FAILURE: 0x00000010 != 0x0000ffef at offset 0x032bce10.
[15:21:57]FAILURE: 0xffffffef != 0xffff0010 at offset 0x032bce11.
[15:21:57]FAILURE: 0x00000010 != 0x0000ffef at offset 0x032bce12.
[15:21:57]FAILURE: 0xffffffef != 0xffff0010 at offset 0x032bce13.
[15:21:57]FAILURE: 0x00000010 != 0x0000ffef at offset 0x032bce14.
[15:21:57]FAILURE: 0xffffffef != 0xffff0010 at offset 0x032bce15.
[15:21:57]FAILURE: 0x00000010 != 0x0000ffef at offset 0x032bce16.
[15:22:49]  Walking Ones        : ok         
[15:23:41]  Walking Zeroes      : ok         
[15:23:41]

0 Kevin S over 5 years ago in reply to gg yang

TI__Mastermind 41780 points

Hi,

Can you please provide the DRAM part #, tool configured for your system, and changes you have made to u-boot related to DDR?

Thanks,
Kevin

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

DRAM： MT41K256M16TW-107 IT

I modified the code :
board\ti\dra7xx\evm.c：

static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x62823332,
.sdram_config = 0x62823332,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x00000A28,
.sdram_tim1 = 0xD333787D,
.sdram_tim2 = 0x40B3802C,
.sdram_tim3 = 0x40BF8AD7,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0E24400F,
.emif_ddr_phy_ctlr_1 = 0x0E24400F,
.emif_rd_wr_exec_thresh = 0x00000305,
#ifdef EMIF_ECC_CTRL_REG_ECC_EN_MASK
.emif_ecc_ctrl_reg = 0x00000000,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
#endif

};

const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
.sdram_config_init = 0x62823332,
.sdram_config = 0x62823332,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x00000A28,
.sdram_tim1 = 0xD333787D,
.sdram_tim2 = 0x40B3802C,
.sdram_tim3 = 0x40BF8AD7,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0E24400F,
.emif_ddr_phy_ctlr_1 = 0x0E24400F,
.emif_rd_wr_exec_thresh = 0x00000305,
#ifdef EMIF_ECC_CTRL_REG_ECC_EN_MASK
.emif_ecc_ctrl_reg = 0x00000000,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
#endif
}

static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
}

arch\arm\cpu\armv7\omap5\hw_data.c

const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrch = 0x40404040,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_lpddr2ch = 0x00404000
.ctrl_emif_sdram_config_ext = 0x0000C123

};

const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrch = 0x40404040,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_lpddr2ch = 0x00404000,
.ctrl_emif_sdram_config_ext = 0x0002C123
};

arch/arm/cpu/armv7/omap5/sdram.c:

const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */
0x006B0085, /* EMIF1_EXT_PHY_CTRL_2 */
0x006B0084, /* EMIF1_EXT_PHY_CTRL_3 */
0x006B008C, /* EMIF1_EXT_PHY_CTRL_4 */
0x006B008A, /* EMIF1_EXT_PHY_CTRL_5 */
0x006B006B, /* EMIF1_EXT_PHY_CTRL_6 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_7 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_8 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_9 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_10 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_11 */
0x0060006D, /* EMIF1_EXT_PHY_CTRL_12 */
0x0060006F, /* EMIF1_EXT_PHY_CTRL_13 */
0x00600072, /* EMIF1_EXT_PHY_CTRL_14 */
0x00600074, /* EMIF1_EXT_PHY_CTRL_15 */
0x00600060, /* EMIF1_EXT_PHY_CTRL_16 */
0x0040004D, /* EMIF1_EXT_PHY_CTRL_17 */
0x0040004F, /* EMIF1_EXT_PHY_CTRL_18 */
0x00400052, /* EMIF1_EXT_PHY_CTRL_19 */
0x00400054, /* EMIF1_EXT_PHY_CTRL_20 */
0x00400040, /* EMIF1_EXT_PHY_CTRL_21 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */
0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */
0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */
0x00000075, /* EMIF1_EXT_PHY_CTRL_26 */
0x00000074, /* EMIF1_EXT_PHY_CTRL_27 */
0x0000007C, /* EMIF1_EXT_PHY_CTRL_28 */
0x0000007A, /* EMIF1_EXT_PHY_CTRL_29 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_30 */
0x0000003D, /* EMIF1_EXT_PHY_CTRL_31 */
0x0000003F, /* EMIF1_EXT_PHY_CTRL_32 */
0x00000042, /* EMIF1_EXT_PHY_CTRL_33 */
0x00000044, /* EMIF1_EXT_PHY_CTRL_34 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_35 */
0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */

};

If the "leveling technique:" S/W "or" H/W "is set to H/W, it cannot be started at normal temperature

EMIF Tools: Register Configuration - Step 2, Board Details

2A is our hardware data。

0 Kevin S over 5 years ago in reply to gg yang

TI__Mastermind 41780 points

Hi,

Thanks for providing the additional information.

>>If the "leveling technique:" S/W "or" H/W "is set to H/W, it cannot be started at normal temperature

Can you also provide the log showing the error when leveling technique is set to "H/W"?

Can you also try clearing the following registers in your configuration to zero to see if this has any impact on the result when using leveling technique "H/W"?

0x00000000, /* EMIF1_EXT_PHY_CTRL_26 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_27 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_28 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_29 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_30 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_31 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_32 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_33 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_34 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_35 */

Thanks,
Kevin

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

HI， Kevin

Modify emif1_ EXT_ PHY_ CTRL, set to HW can start, but the test is abnormal at low temperature.

dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2{

0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */
0x006B0085, /* EMIF1_EXT_PHY_CTRL_2 */
0x006B0084, /* EMIF1_EXT_PHY_CTRL_3 */
0x006B008C, /* EMIF1_EXT_PHY_CTRL_4 */
0x006B008A, /* EMIF1_EXT_PHY_CTRL_5 */
0x006B006B, /* EMIF1_EXT_PHY_CTRL_6 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_7 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_8 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_9 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_10 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_11 */
0x0060006D, /* EMIF1_EXT_PHY_CTRL_12 */
0x0060006F, /* EMIF1_EXT_PHY_CTRL_13 */
0x00600072, /* EMIF1_EXT_PHY_CTRL_14 */
0x00600074, /* EMIF1_EXT_PHY_CTRL_15 */
0x00600060, /* EMIF1_EXT_PHY_CTRL_16 */
0x0040004D, /* EMIF1_EXT_PHY_CTRL_17 */
0x0040004F, /* EMIF1_EXT_PHY_CTRL_18 */
0x00400052, /* EMIF1_EXT_PHY_CTRL_19 */
0x00400054, /* EMIF1_EXT_PHY_CTRL_20 */
0x00400040, /* EMIF1_EXT_PHY_CTRL_21 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */
0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */
0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */
0x00000075, /* EMIF1_EXT_PHY_CTRL_26 */
0x00000074, /* EMIF1_EXT_PHY_CTRL_27 */
0x0000007C, /* EMIF1_EXT_PHY_CTRL_28 */
0x0000007A, /* EMIF1_EXT_PHY_CTRL_29 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_30 */
0x0000003D, /* EMIF1_EXT_PHY_CTRL_31 */
0x0000003F, /* EMIF1_EXT_PHY_CTRL_32 */
0x00000042, /* EMIF1_EXT_PHY_CTRL_33 */
0x00000044, /* EMIF1_EXT_PHY_CTRL_34 */
0x00000000, /* EMIF1_EXT_PHY_CTRL_35 */
0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */

}

const struct emif_regs DRA72x_DDR3L_666MHz_emif_regs = {

.sdram_config_init = 0x62823332,
.sdram_config = 0x62823332,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x00000A25,
.sdram_tim1 = 0xD333787C,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x407F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400F,
.emif_ddr_phy_ctlr_1 = 0x0E24400F,
.emif_rd_wr_exec_thresh = 0x00000305,
#ifdef EMIF_ECC_CTRL_REG_ECC_EN_MASK
.emif_ecc_ctrl_reg = 0x00000000,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
#endif

}

root@dra7xx-evm:/datafs# ./memtester 500M 20
memtester version 4.1.3 (32-bit)
Copyright (C) 2010 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

Loop 2/20:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : testing 47FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d48810.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d48811.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d48812.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d48813.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d48814.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d48815.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d48816.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d48817.
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : testing 78FAILURE: 0xffff0200 != 0xfffffdff at offset 0x01a04410.
FAILURE: 0x0000fdff != 0x00000200 at offset 0x01a04411.
FAILURE: 0xffff0200 != 0xfffffdff at offset 0x01a04412.
FAILURE: 0x0000fdff != 0x00000200 at offset 0x01a04413.
FAILURE: 0xffff0200 != 0xfffffdff at offset 0x01a04414.
FAILURE: 0x0000fdff != 0x00000200 at offset 0x01a04415.
FAILURE: 0xffff0200 != 0xfffffdff at offset 0x01a04416.
FAILURE: 0x0000fdff != 0x00000200 at offset 0x01a04417

0 gg yang over 5 years ago in reply to gg yang

Expert 1310 points

root@dra7xx-evm:/datafs# ./memtester 500M 20
memtester version 4.1.3 (32-bit)
Copyright (C) 2010 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

pagesize is 4096
pagesizemask is 0xfffff000
want 500MB (524288000 bytes)
got 500MB (524288000 bytes), trying mlock ...locked.
Loop 1/20:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : testing 4FAILURE: 0xffff0000 != 0xffffffff at offset 0x02a75e10.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x02a75e11.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x02a75e12.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x02a75e13.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x02a75e14.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x02a75e15.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x02a75e16.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x02a75e17.
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : testing 62FAILURE: 0x00000080 != 0x0000ff7f at offset 0x0053ca0f.
FAILURE: 0xffffff7f != 0xffff0080 at offset 0x0053ca10.
FAILURE: 0x00000080 != 0x0000ff7f at offset 0x0053ca11.
FAILURE: 0xffffff7f != 0xffff0080 at offset 0x0053ca12.
FAILURE: 0x00000080 != 0x0000ff7f at offset 0x0053ca13.
FAILURE: 0xffffff7f != 0xffff0080 at offset 0x0053ca14.
FAILURE: 0x00000080 != 0x0000ff7f at offset 0x0053ca15.
FAILURE: 0xffffff7f != 0xffff0080 at offset 0x0053ca16.
Walking Ones : ok
Walking Zeroes : ok

Loop 2/20:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : ok
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : ok
Walking Ones : ok
Walking Zeroes : ok

Loop 3/20:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : testing 22FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7b810.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7b811.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7b812.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7b813.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7b814.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7b815.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7b816.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7b817.
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : testing 18FAILURE: 0xffff0004 != 0xfffffffb at offset 0x0322e410.
FAILURE: 0x0000fffb != 0x00000004 at offset 0x0322e411.
FAILURE: 0xffff0004 != 0xfffffffb at offset 0x0322e412.
FAILURE: 0x0000fffb != 0x00000004 at offset 0x0322e413.
FAILURE: 0xffff0004 != 0xfffffffb at offset 0x0322e414.
FAILURE: 0x0000fffb != 0x00000004 at offset 0x0322e415.
FAILURE: 0xffff0004 != 0xfffffffb at offset 0x0322e416.
FAILURE: 0x0000fffb != 0x00000004 at offset 0x0322e417.
Walking Ones : ok
Walking Zeroes : ok

Loop 4/20:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : testing 25FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7f810.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7f811.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7f812.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7f813.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7f814.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7f815.
FAILURE: 0x0000ffff != 0x00000000 at offset 0x00d7f816.
FAILURE: 0xffff0000 != 0xffffffff at offset 0x00d7f817.
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : testing 81FAILURE: 0x0000fbff != 0x00000400 at offset 0x00d34810.
FAILURE: 0xffff0400 != 0xfffffbff at offset 0x00d34811.
FAILURE: 0x0000fbff != 0x00000400 at offset 0x00d34812.
FAILURE: 0xffff0400 != 0xfffffbff at offset 0x00d34813.
FAILURE: 0x0000fbff != 0x00000400 at offset 0x00d34814.
FAILURE: 0xffff0400 != 0xfffffbff at offset 0x00d34815.
FAILURE: 0x0000fbff != 0x00000400 at offset 0x00d34816.
FAILURE: 0xffff0400 != 0xfffffbff at offset 0x00d34817.

0 Kevin S over 5 years ago in reply to gg yang

TI__Mastermind 41780 points

Hi,

I am trying to ensure I have the correct understanding.

Previously, you wrote:

If the configuration is hw, it can not be started at normal temperature.

When the configuration is SW, it can start at low temperature, but there is abnormality,

Now, you wrote:

Modify emif1_ EXT_ PHY_ CTRL, set to HW can start, but the test is abnormal at low temperature.

Does this imply that by clearing EMIF1_EXT_PHY_CTRL_26 - EMIF1_EXT_PHY_CTRL_35 to 0x0 the test case improved? Does it also imply that you now obtain the same results for both "HW" or "SW" leveling techniques?

Based on the failures you have shown, this looks like an addressing issue. As an experiment, can you try the following two settings?

Set EMIF1_EXT_PHY_CTRL_1 to 0x040300C0
Set EMIF1_EXT_PHY_CTRL_1 to 0x04050140

Also, do you know whether the command and address signals are skew matched to clock?

Regards,
Kevin

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

HI.Kevin

Previously set to HW, unable to start because emif1_ EXT_ PHY_ CTRL configuration is wrong, and the call is not the PY configuration generated by avatar_ EMIF_ RegisterConfigt.xlsm. After modification, it can be started if the configuration is hw.。

Now set to HW,

Set EMIF1_EXT_PHY_CTRL_1 to 0x040300C0

Some boards are normally tested with memtester at low and high temperatures。

Some boards can't start, and there is no log output.

If set to emif1_ EXT_ PHY_ CTRL_ 1 to 0x 04040100 can be started again.Kernel started up normally。

if Set EMIF1_EXT_PHY_CTRL_1 to 0x04050140 Uboot can start, but the kernel is abnorma

log::

U-Boot SPL 2016.05-svn22895 (Nov 12 2020 - 19:45:58)
DRA722-GP ES2.1
Trying to boot from MMC1
no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
reading u-boot.img
reading u-boot.img

U-Boot 2016.05-svn22895 (Nov 12 2020 - 19:45:58 +0800)

CPU : DRA722-GP ES2.1
Model: TI DRA71 EVM
Board: DRA71x EVM REV C.1
I2C: ready
DRAM: 534s 3 >>sdram_init()
1 GiB
MMC: no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment

PRM_RSTST is 1
reset reason:1
GLOBAL_COLD_RST ...
reading zeus_update/update.scr
** Unable to read file zeus_update/update.scr **
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
reading uEnv.txt
215 bytes read in 2 ms (104.5 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
4313984 bytes read in 199 ms (20.7 MiB/s)
94083 bytes read in 14 ms (6.4 MiB/s)
Booting from mmc0 ...
Kernel image @ 0x82000000 [ 0x000000 - 0x41d380 ]
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe6000, end 8fffff82 ... OK

Starting kernel ...

[ 0.000000] ------------[ cut here ]------------
[ 0.000000] Kernel BUG at c002a8a0 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.84 #128
[ 0.000000] Hardware name: Generic DRA72X (Flattened Device Tree)
[ 0.000000] task: c0779878 ti: c0774000 task.ti: c0774000
[ 0.000000] PC is at omap4_prminst_read_inst_reg.part.0+0xc/0x10
[ 0.000000] LR is at omap4_prminst_write_inst_reg+0x0/0x40
[ 0.000000] pc : [<c002a8a0>] lr : [<c002a954>] psr: 600000d3
[ 0.000000] sp : c0775e78 ip : c0775e88 fp : c0775e84
[ 0.000000] r10: c075b600 r9 : 00000000 r8 : 000186a1
[ 0.000000] r7 : c0790ef8 r6 : 0001a36e r5 : c077d7c8 r4 : 00000001
[ 0.000000] r3 : 00000000 r2 : 00000004 r1 : 00000f00 r0 : 00000001
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 30c5387d Table: 80003000 DAC: fffffffd
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc0774210)
[ 0.000000] Stack: (0xc0775e78 to 0xc0776000)
[ 0.000000] 5e60: c0775e94 c0775e88
[ 0.000000] 5e80: c002a954 c002a8a0 c0775ebc c0775e98 c002a6e0 c002a920 c077d7c8 c077c2e8
[ 0.000000] 5ea0: c07661e4 c07b8b10 c06915e0 00000000 c0775ee4 c0775ec0 c002b9d4 c002a698
[ 0.000000] 5ec0: c077958c 00000000 00000000 00000000 c07765c0 00000000 c0775ef4 c0775ee8
[ 0.000000] 5ee0: c0737cfc c002b8c0 c0775f0c c0775ef8 c0732468 c0737ce4 00000000 c075b600
[ 0.000000] 5f00: c0775f9c c0775f10 c072ca10 c0732434 00000000 00000000 00000000 00000000
[ 0.000000] 5f20: ffffffff 00000000 c073d024 c077a9a8 bfcfffff 00000000 bfd00000 00000000
[ 0.000000] 5f40: 000bfd00 00000000 00080000 00000000 80000000 00000000 00000000 00000000
[ 0.000000] 5f60: 00000000 00000000 00000000 00000000 c0775f9c 00000000 00008000 00000000
[ 0.000000] 5f80: 00000000 ffffffff c0776400 00000000 c0775ff4 c0775fa0 c0729a34 c072bf0c
[ 0.000000] 5fa0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.000000] 5fc0: 00000000 c0762a28 00000000 c07b8214 c0776484 c0762a24 c077aaf8 80007000
[ 0.000000] 5fe0: 412fc0f2 00000000 00000000 c0775ff8 80008090 c0729994 00000000 00000000
[ 0.000000] Backtrace:
[ 0.000000] [<c002a894>] (omap4_prminst_read_inst_reg.part.0) from [<c002a954>] (omap4_prminst_write_inst_reg+0x0/0x40)
[ 0.000000] [<c002a914>] (omap4_prminst_read_inst_reg) from [<c002a6e0>] (omap4_pwrdm_wait_transition+0x54/0x80)
[ 0.000000] [<c002a68c>] (omap4_pwrdm_wait_transition) from [<c002b9d4>] (pwrdm_register_pwrdms+0x120/0x180)
[ 0.000000] r9:00000000 r8:c06915e0 r7:c07b8b10 r6:c07661e4 r5:c077c2e8 r4:c077d7c8
[ 0.000000] [<c002b8b4>] (pwrdm_register_pwrdms) from [<c0737cfc>] (dra7xx_powerdomains_init+0x24/0x88)
[ 0.000000] r9:00000000 r8:c07765c0 r7:00000000 r6:00000000 r5:00000000 r4:c077958c
[ 0.000000] [<c0737cd8>] (dra7xx_powerdomains_init) from [<c0732468>] (dra7xx_init_early+0x40/0x80)
[ 0.000000] [<c0732428>] (dra7xx_init_early) from [<c072ca10>] (setup_arch+0xb10/0xb3c)
[ 0.000000] [<c072bf00>] (setup_arch) from [<c0729a34>] (start_kernel+0xac/0x40c)
[ 0.000000] r10:00000000 r9:c0776400 r8:ffffffff r7:00000000 r6:00000000 r5:00008000
[ 0.000000] r4:00000000
[ 0.000000] [<c0729988>] (start_kernel) from [<80008090>] (0x80008090)
[ 0.000000] r10:00000000 r9:412fc0f2 r8:80007000 r7:c077aaf8 r6:c0762a24 r5:c0776484
[ 0.000000] r4:c07b8214
[ 0.000000] Code: e89da800 e1a0c00d e92dd800 e24cb004 (e7f001f2)
[ 0.000000] ---[ end trace cb88537fdc8fa200 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!

U-Boot SPL 2016.05-svn22895 (Nov 12 2020 - 19:46:58)
DRA722-GP ES2.1
Trying to boot from MMC1
no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
reading u-boot.img
reading u-boot.img

U-Boot 2016.05-svn22895 (Nov 12 2020 - 19:46:58 +0800)

PRM_RSTST is 1
reset reason:1
GLOBAL_COLD_RST ...
reading zeus_update/update.scr
** Unable to read file zeus_update/update.scr **
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
reading uEnv.txt
215 bytes read in 3 ms (69.3 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
4313984 bytes read in 200 ms (20.6 MiB/s)
94083 bytes read in 14 ms (6.4 MiB/s)
Booting from mmc0 ...
Kernel image @ 0x82000000 [ 0x000000 - 0x41d380 ]
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe6000, end 8fffff82 ... OK

Starting kernel ...

U-Boot SPL 2016.05-svn22895 (Nov 12 2020 - 19:46:58)
DRA722-GP ES2.1
Trying to boot from MMC1
no pinctrl for hs200_1_8v
no pinctrl for ddr_1_8v
reading u-boot.img
reading u-boot.img

U-Boot 2016.05-svn22895 (Nov 12 2020 - 19:46:58 +0800)

PRM_RSTST is 1
reset reason:1
GLOBAL_COLD_RST ...
reading zeus_update/update.scr
** Unable to read file zeus_update/update.scr **
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
reading uEnv.txt
215 bytes read in 3 ms (69.3 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
4313984 bytes read in 200 ms (20.6 MiB/s)
94083 bytes read in 14 ms (6.4 MiB/s)
Booting from mmc0 ...
Kernel image @ 0x82000000 [ 0x000000 - 0x41d380 ]
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe6000, end 8fffff82 ... OK

Starting kernel ...

-->>>625
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] Kernel BUG at c002a8a0 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.84 #128
[ 0.000000] Hardware name: Generic DRA72X (Flattened Device Tree)
[ 0.000000] task: c0779878 ti: c0774000 task.ti: c0774000
[ 0.000000] PC is at omap4_prminst_read_inst_reg.part.0+0xc/0x10
[ 0.000000] LR is at omap4_prminst_write_inst_reg+0x0/0x40
[ 0.000000] pc : [<c002a8a0>] lr : [<c002a954>] psr: 600000d3
[ 0.000000] sp : c0775e78 ip : c0775e88 fp : c0775e84
[ 0.000000] r10: c075b600 r9 : 00000000 r8 : 000186a1
[ 0.000000] r7 : c0790ef8 r6 : 0001a36e r5 : c077d7c8 r4 : 00000001
[ 0.000000] r3 : 00000000 r2 : 00000004 r1 : 00000f00 r0 : 00000001
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 30c5387d Table: 80003000 DAC: fffffffd
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc0774210)
[ 0.000000] Stack: (0xc0775e78 to 0xc0776000)
[ 0.000000] 5e60: c0775e94 c0775e88
[ 0.000000] 5e80: c002a954 c002a8a0 c0775ebc c0775e98 c002a6e0 c002a920 c077d7c8 c077c2e8
[ 0.000000] 5ea0: c07661e4 c07b8b10 c06915e0 00000000 c0775ee4 c0775ec0 c002b9d4 c002a698
[ 0.000000] 5ec0: c077958c 00000000 00000000 00000000 c07765c0 00000000 c0775ef4 c0775ee8
[ 0.000000] 5ee0: c0737cfc c002b8c0 c0775f0c c0775ef8 c0732468 c0737ce4 00000000 c075b600
[ 0.000000] 5f00: c0775f9c c0775f10 c072ca10 c0732434 00000000 00000000 00000000 00000000
[ 0.000000] 5f20: ffffffff 00000000 c073d024 c077a9a8 bfcfffff 00000000 bfd00000 00000000
[ 0.000000] 5f40: 000bfd00 00000000 00080000 00000000 80000000 00000000 00000000 00000000
[ 0.000000] 5f60: 00000000 00000000 00000000 00000000 c0775f9c 00000000 00008000 00000000
[ 0.000000] 5f80: 00000000 ffffffff c0776400 00000000 c0775ff4 c0775fa0 c0729a34 c072bf0c
[ 0.000000] 5fa0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.000000] 5fc0: 00000000 c0762a28 00000000 c07b8214 c0776484 c0762a24 c077aaf8 80007000
[ 0.000000] 5fe0: 412fc0f2 00000000 00000000 c0775ff8 80008090 c0729994 00000000 00000000
[ 0.000000] Backtrace:
[ 0.000000] [<c002a894>] (omap4_prminst_read_inst_reg.part.0) from [<c002a954>] (omap4_prminst_write_inst_reg+0x0/0x40)
[ 0.000000] [<c002a914>] (omap4_prminst_read_inst_reg) from [<c002a6e0>] (omap4_pwrdm_wait_transition+0x54/0x80)
[ 0.000000] [<c002a68c>] (omap4_pwrdm_wait_transition) from [<c002b9d4>] (pwrdm_register_pwrdms+0x120/0x180)
[ 0.000000] r9:00000000 r8:c06915e0 r7:c07b8b10 r6:c07661e4 r5:c077c2e8 r4:c077d7c8
[ 0.000000] [<c002b8b4>] (pwrdm_register_pwrdms) from [<c0737cfc>] (dra7xx_powerdomains_init+0x24/0x88)
[ 0.000000] r9:00000000 r8:c07765c0 r7:00000000 r6:00000000 r5:00000000 r4:c077958c
[ 0.000000] [<c0737cd8>] (dra7xx_powerdomains_init) from [<c0732468>] (dra7xx_init_early+0x40/0x80)
[ 0.000000] [<c0732428>] (dra7xx_init_early) from [<c072ca10>] (setup_arch+0xb10/0xb3c)
[ 0.000000] [<c072bf00>] (setup_arch) from [<c0729a34>] (start_kernel+0xac/0x40c)
[ 0.000000] r10:00000000 r9:c0776400 r8:ffffffff r7:00000000 r6:00000000 r5:00008000
[ 0.000000] r4:00000000
[ 0.000000] [<c0729988>] (start_kernel) from [<80008090>] (0x80008090)
[ 0.000000] r10:00000000 r9:412fc0f2 r8:80007000 r7:c077aaf8 r6:c0762a24 r5:c0776484
[ 0.000000] r4:c07b8214
[ 0.000000] Code: e89da800 e1a0c00d e92dd800 e24cb004 (e7f001f2)
[ 0.000000] ---[ end trace cb88537fdc8fa200 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!

0 Kevin S over 5 years ago in reply to gg yang

TI__Mastermind 41780 points

Hi,

You mention below that "some boards can't start, and there is no log output". Do these boards start when you use a different EMIF1_EXT_PHY_CTRL_1 register setting? Typically, u-boot will output some info before DDR is configured, so my assumption is that if you are not seeing any output at all, than the issue may not be DDR related. Discarding these boards which show no output, is my understanding correct that using EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 fixes the issue?

gj y said:

Set EMIF1_EXT_PHY_CTRL_1 to 0x040300C0

Some boards are normally tested with memtester at low and high temperatures。

Some boards can't start, and there is no log output.

If set to emif1_ EXT_ PHY_ CTRL_ 1 to 0x 04040100 can be started again.Kernel started up normally。

if Set EMIF1_EXT_PHY_CTRL_1 to 0x04050140 Uboot can start, but the kernel is abnorma

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

HI.

These boards Set EMIF1_EXT_PHY_CTRL_1 to 04040100 can start， EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 can't start , no log output.

Set EMIF1_EXT_PHY_CTRL_1 to 0x04050140 Uboot can start, but the kernel is abnorma.

Discarding these boards which show no output ，using EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 fixes the issue。

If is set EMIF1_EXT_PHY_CTRL_1 to 0x04050140, all five boards can be started.

if using EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 Two boards were tested at high and low temperatures can start. fixes the issue.

0 gg yang over 5 years ago in reply to Kevin S

Expert 1310 points

HI.

These boards Set EMIF1_EXT_PHY_CTRL_1 to 04040100 can start， EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 can't start , no log output.
Set EMIF1_EXT_PHY_CTRL_1 to 0x04050140 Uboot can start, but the kernel is abnorma.

Discarding these boards which show no output ，Two boards using EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 fixes the issue。
If is set EMIF1_EXT_PHY_CTRL_1 to 0x04050140, all five boards can be started.

if using EMIF1_EXT_PHY_CTRL_1 = 0x040300C0 Two boards were tested at high and low temperatures can start. fixes the issue.

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