Part Number: AM3352
Tool/software: TI C/C++ Compiler
Hi
I am working on a board loosely based on the BeagleBoneBlack
presently this boots and runs from a single SPI flash ROM defined via the following entries in the device tree:
&am33xx_pinmux {
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 (MUX_MODE0 | PIN_INPUT_PULLUP) /*0x30*/
0x154 (MUX_MODE0 | PIN_INPUT_PULLUP) /*0x30*/
0x158 (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*0x10*/
0x15c (MUX_MODE0 | PIN_OUTPUT_PULLUP)/*0x10 SPI0 CS0 */
>;
};
}
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
u-boot,dm-spl;
spi-flash@0 {
u-boot,dm-spl;
compatible = "micron,n25q256a","jedec,spi-nor";
spi-max-frequency = <48000000>;
status = "okay";
reg = <0>;
m25p,fast-read;
#address-cells = <1>;
#size-cells = <1>;
partition@0x0000 { label="SPL"; reg = <0x0000 0x20000>; };
partition@0x20000 { label="u-boot"; reg = <0x20000 0x100000>; };
partition@0x120000 { label="dtb"; reg = <0x120000 0x20000>; };
partition@0x140000 { label="kernel"; reg = <0x140000 0x600000>; };
partition@0x740000 { label="rootfs"; reg = <0x740000 0xb00000>; };
partition@0x1240000{ label="spare"; reg = <0x1240000 0xb00000>; };
partition@0x1D40000{ label="config"; reg = <0x1D40000 0x2c0000>; };
};
};
in an upcoming rev to the board there will be a secondary chip added to this bus making use of the native SPI0_CS1 on the chip
what I am unsure of is how to distinguish these two chips in the device tree
as the pins are defined with respect to the bus I expect the following needs added to the pins definition
0x160 (MUX_MODE0 | PIN_OUTPUT_PULLUP) /*0x10 SPI0 CS1*/
Is the native CS to be used inferred from the the node name i.e.
spi-flash@0 = CS 0
spi-flash@1 = CS 1
if this is not the case I would be grateful if someone could explain the correct syntax .
All the best
- Richard
