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AM4376: Help with USB uBoot bringup

Part Number: AM4376

Hello all,

Trying to bring USB up so I can use DFU to flash an embedded MMC in our custom board based on the AM437x EVM SK. Both USBs are configured as host, upon `usb start`, I'm getting the following

Please note that I added additional printf instructions to try and figure out where exactly the problem is happening, that's why you will see a slightly more verbose output to usb start.

=> usb start
starting USB...
USB0:   generic_phy_get_by_index(dev=8df418e8, index=0, phy=8df43840)
Looking for phy@483a8000
generic_phy_get_by_index: uclass_get_device_by_ofnode failed: err=-19
Looking for ocp2scp@483a8000
Failed to get USB PHY0 for usb@48390000
Port not available.
USB1:   generic_phy_get_by_index(dev=8df419e0, index=0, phy=8df438c0)
Looking for phy@483e8000
generic_phy_get_by_index: uclass_get_device_by_ofnode failed: err=-19
Looking for ocp2scp@483e8000
Failed to get USB PHY0 for usb@483d0000
Port not available.

I added the following to the custom board dts:

boot_usb_ms_pins_default: boot_usb_ms_pins_default {
		pinctrl-single,pins = <
			AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* (F25) USB1_DRVVBUS.USB1_DRVVBUS */
		>;
	};

	lte_usb_pins_default: lte_usb_pins_default {
		pinctrl-single,pins = <
			AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* (G21) USB0_DRVVBUS.USB0_DRVVBUS */
		>;
	};

&usb2_phy1 {
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&lte_usb_pins_default>;
};

&usb2_phy2 {
	status = "okay";
};

&usb2 {
	dr_mode = "host";
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&boot_usb_ms_pins_default>;
};

Any idea what might be happening here?

Thank you in advance!

  • Hi Kamil,

    Kamil Muza1 said:
    Trying to bring USB up so I can use DFU to flash an embedded MMC in our custom board based on the AM437x EVM SK.

    Please note that AM437x ROM doesn't support DFU, the USB client boot mode is USB-Ethernet, please refer to TRM section 5.2.7.5. USB Client (USB_CL) Boot Procedure for details.

    Kamil Muza1 said:
    Both USBs are configured as host,

    To use USB client boot, the USB0 port has to be configured in peripheral mode.

    Kamil Muza1 said:
    I added the following to the custom board dts:

    Are you using Processor SDK release? Which version is it?

  • I must have interpreted the DFU process wrong, however, there must be a way to copy the uboot img and spl to the emmc using usb 1 in host mode and attaching a mass storage right?

    Regarding the DTS, im using processor sdk 06.03.00. My goal is to flash the eMMC, so far i can boot into uboot using uart0, only, i have no other peripheral working yet. (Aside from the emmc), i do not have an sd card slot on the custom board.

  • Kamil,

    Yes, AM437x supports boot from USB mass storage device via USB1 port, the TRM section 5.2.6.8.("USB Mass Sorage (USB_MS) Device" has the details.

    You don't need UART boot in this case because AM437x ROM can directly boot from USB mass storage device.

    Booting from USB mass storage device is very similar to boot from SD card, you prepare the thumb drive in the same way as SD card - copying MLO and u-boot,img to the first partition, and copying Linux rootfs to the second partition, specify the linux root device is /dev/sda2 in uboot bootargs.

    Then set your board SYSBOOT mode to boot from USB_MS, your board should boot into linux from the thumb drive, then you can use the LInux utilities to partition and format the eMMC, and copy over all the Linux files.

  • Bin Liu said:

    Kamil,

    Yes, AM437x supports boot from USB mass storage device via USB1 port, the TRM section 5.2.6.8.("USB Mass Sorage (USB_MS) Device" has the details.

    You don't need UART boot in this case because AM437x ROM can directly boot from USB mass storage device.

    Booting from USB mass storage device is very similar to boot from SD card, you prepare the thumb drive in the same way as SD card - copying MLO and u-boot,img to the first partition, and copying Linux rootfs to the second partition, specify the linux root device is /dev/sda2 in uboot bootargs.

    Then set your board SYSBOOT mode to boot from USB_MS, your board should boot into linux from the thumb drive, then you can use the LInux utilities to partition and format the eMMC, and copy over all the Linux files.

     

    Great. Do you have any input in why the board USBs are not starting when I perform usb start? Is there any extra information that I should post to possibly identify the problem?

  • The AM437x EVM SK uses the USB1 port in host mode, so you can refer to the SK board DTS in uboot without any changes, your board USB1 should work in host mode.

    If "usb start" or "usb reset" command still doesn't detect a thumb drive, we would have to first review your board USB schematics; if no issue there, you need to figure out a way to boot your board in Linux then we can debug your USB in Linux. Debugging USB in Linux is much easier then in U-Boot.

  • Bin Liu said:

    The AM437x EVM SK uses the USB1 port in host mode, so you can refer to the SK board DTS in uboot without any changes, your board USB1 should work in host mode.

    I pretty much followed the am437x evm sk usb dts config, with the exception that I configured usb0 as host as well (Because this usb is a fixed host usb that will hold an LTE card). Should I turn off USB0 for now until I get USB1 to work?

    Bin Liu said:

    If "usb start" or "usb reset" command still doesn't detect a thumb drive, we would have to first review your board USB schematics; if no issue there, you need to figure out a way to boot your board in Linux then we can debug your USB in Linux. Debugging USB in Linux is much easier then in U-Boot.

    Please see attached the schematics of both USBs. usb start keeps failing with an attached thumbdrive with the boot partition formated in vfat containing the MLO and u-boot.img.

    See the logs

    => usb start
    starting USB...
    Init low level USB USB0
    :   Before device probe
    generic_phy_get_by_index(dev=8df418e8, index=0, phy=8df41fc0)
    Looking for phy@483a8000
    generic_phy_get_by_index: uclass_get_device_by_ofnode failed: err=-19
    Looking for ocp2scp@483a8000
    Failed to get USB PHY0 for usb@48390000
    Port not available.
    Init low level USB USB1
    :   Before device probe
    generic_phy_get_by_index(dev=8df419e0, index=0, phy=8df42040)
    Looking for phy@483e8000
    generic_phy_get_by_index: uclass_get_device_by_ofnode failed: err=-19
    Looking for ocp2scp@483e8000
    Failed to get USB PHY0 for usb@483d0000
    Port not available.

    usb_schematic.pdf



    Thank you!

  • Kamil Muza1 said:
    I pretty much followed the am437x evm sk usb dts config, with the exception that I configured usb0 as host as well (Because this usb is a fixed host usb that will hold an LTE card). Should I turn off USB0 for now until I get USB1 to work?

    Yes, please change USB0 back to peripheral mode in UBoot for now. UBoot only supports one USB host. If you configured both USB ports to be host, 'usb start' will only try to start the first port, which is USB0. And I guess the failure log is because you didn't do all the changes which are required for USB0 to work in host mode. So please change USB0 back to peripheral mode, so that we can make USB1 boot work first.

  • Bin Liu said:

    Yes, please change USB0 back to peripheral mode in UBoot for now. UBoot only supports one USB host. If you configured both USB ports to be host, 'usb start' will only try to start the first port, which is USB0. And I guess the failure log is because you didn't do all the changes which are required for USB0 to work in host mode. So please change USB0 back to peripheral mode, so that we can make USB1 boot work first.



    I have changed USB0 back to peripheral like so:

    &usb2_phy1 {
    	status = "okay";
    };
    
    &usb1 {
    	dr_mode = "peripheral";
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&lte_usb_pins_default>;
    };

    Unfortunately, I keep getting the same error, but now it's only attempting to load one USB (which by the looks of it is USB1)

    => usb start
    starting USB...
    Init low level USB USB0
    :   Before device probe
    generic_phy_get_by_index(dev=8df41a00, index=0, phy=8df43680)
    Looking for phy@483e8000
    generic_phy_get_by_index: uclass_get_device_by_ofnode failed: err=-19
    Looking for ocp2scp@483e8000
    Failed to get USB PHY0 for usb@483d0000
    Port not available.
    =>

    Why exactly is it saying PHY0 and USB0 while showing the addresses of the ocp2scp and phy of USB1? 
    Do you recognize this type of error? err=-19?

    Please see attached my defconfig and dtb

    Is there any other step that needs to be performed to bring USB up in uboot other than adding the correct DTS settings?

    For some reason I cant upload this files, see them below

    CONFIG_ARM=y
    CONFIG_ARCH_OMAP2PLUS=y
    CONFIG_TI_COMMON_CMD_OPTIONS=y
    CONFIG_SYS_MALLOC_F_LEN=0x2000
    CONFIG_AM43XX=y
    CONFIG_TARGET_AM43XX_HUBPLUS=y
    CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
    CONFIG_SPL=y
    CONFIG_DISTRO_DEFAULTS=y
    CONFIG_SPL_LOAD_FIT=y
    CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
    # CONFIG_USE_BOOTCOMMAND is not set
    CONFIG_LOG=y
    CONFIG_SPL_LOG=y
    CONFIG_LOG_ERROR_RETURN=y
    CONFIG_LOG_CONSOLE=y
    CONFIG_MAX_LOG_LEVEL=5
    CONFIG_SYS_CONSOLE_INFO_QUIET=y
    # CONFIG_MISC_INIT_R is not set
    CONFIG_VERSION_VARIABLE=y
    CONFIG_SPL_ETH_SUPPORT=y
    CONFIG_SPL_MTD_SUPPORT=y
    CONFIG_SPL_NET_SUPPORT=y
    CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
    CONFIG_SPL_OS_BOOT=y
    CONFIG_SPL_USB_GADGET=y
    CONFIG_SPL_USB_ETHER=y
    #CONFIG_SPL_USB_HOST_SUPPORT=y
    #CONFIG_SPL_USB_SUPPORT=y
    CONFIG_CMD_SPL=y
    CONFIG_CMD_SPL_NAND_OFS=0x00100000
    CONFIG_CMD_SPL_WRITE_SIZE=0x40000
    # CONFIG_CMD_FLASH is not set
    CONFIG_CMD_NAND=y
    # CONFIG_CMD_SETEXPR is not set
    CONFIG_CMD_MTDPARTS=y
    CONFIG_CMD_DM=y
    CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
    CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
    CONFIG_OF_CONTROL=y
    CONFIG_DEFAULT_DEVICE_TREE="am437x-hubplus"
    # CONFIG_ENV_IS_IN_FAT is not set
    #CONFIG_ENV_IS_IN_MMC=y
    CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
    CONFIG_DM=y
    CONFIG_REGMAP=y
    CONFIG_SPL_REGMAP=y
    CONFIG_SYSCON=y
    CONFIG_SPL_SYSCON=y
    CONFIG_DFU_MMC=y
    CONFIG_DFU_RAM=y
    CONFIG_DFU_SF=y
    CONFIG_DM_GPIO=y
    CONFIG_MISC=y
    CONFIG_DM_MMC=y
    CONFIG_MMC_OMAP_HS=y
    CONFIG_NAND=y
    CONFIG_SPI_FLASH=y
    CONFIG_SPI_FLASH_MACRONIX=y
    CONFIG_PHY_GIGE=y
    CONFIG_MII=y
    CONFIG_DRIVER_TI_CPSW=y
    CONFIG_PHY=y
    CONFIG_SPL_PHY=y
    CONFIG_OMAP_USB2_PHY=y
    CONFIG_DM_SERIAL=y
    CONFIG_SPI=y
    CONFIG_TI_QSPI=y
    CONFIG_TIMER=y
    CONFIG_OMAP_TIMER=y
    CONFIG_USB=y
    CONFIG_DM_USB=y
    CONFIG_DM_USB_GADGET=y
    CONFIG_SPL_DM_USB_GADGET=y
    CONFIG_USB_XHCI_HCD=y
    CONFIG_USB_XHCI_DWC3=y
    CONFIG_USB_DWC3=y
    CONFIG_USB_DWC3_GADGET=y
    CONFIG_USB_DWC3_OMAP=y
    CONFIG_USB_DWC3_GENERIC=y
    CONFIG_USB_DWC3_PHY_OMAP=y
    CONFIG_OMAP_USB_PHY=y
    CONFIG_USB_GADGET=y
    CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
    CONFIG_USB_GADGET_VENDOR_NUM=0x0403
    CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
    CONFIG_USB_GADGET_DOWNLOAD=y
    CONFIG_USB_ETHER=y
    CONFIG_CLK=y
    CONFIG_CLK_CDCE9XX=y
    CONFIG_DEBUG_UART_BASE=0x44e09000
    CONFIG_DEBUG_UART_CLOCK=48000000
    CONFIG_DEBUG_UART=y
    CONFIG_DEBUG_UART_OMAP=y
    CONFIG_DEBUG_UART_SHIFT=2
    CONFIG_DEBUG_UART_ANNOUNCE=y
    
    /dts-v1/;
    
    / {
    	#address-cells = <0x1>;
    	#size-cells = <0x1>;
    	compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43";
    	interrupt-parent = <0x1>;
    	model = "TI AM437x HUBPLUS";
    
    	chosen {
    		stdout-path = "/ocp/serial@44e09000";
    	};
    
    	aliases {
    		i2c0 = "/ocp/i2c@44e0b000";
    		i2c1 = "/ocp/i2c@4802a000";
    		i2c2 = "/ocp/i2c@4819c000";
    		serial0 = "/ocp/serial@44e09000";
    		ethernet0 = "/ocp/ethernet@4a100000/slave@4a100200";
    		ethernet1 = "/ocp/ethernet@4a100000/slave@4a100300";
    		spi0 = "/ocp/qspi@47900000";
    	};
    
    	memory {
    		device_type = "memory";
    		reg = <0x0 0x0>;
    	};
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x0>;
    			clocks = <0x2>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			phandle = <0x41>;
    		};
    	};
    
    	interrupt-controller@48241000 {
    		compatible = "arm,cortex-a9-gic";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x48241000 0x1000 0x48240100 0x100>;
    		interrupt-parent = <0x3>;
    		phandle = <0x3>;
    	};
    
    	interrupt-controller@48281000 {
    		compatible = "ti,omap4-wugen-mpu";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x48281000 0x1000>;
    		interrupt-parent = <0x3>;
    		phandle = <0x1>;
    	};
    
    	l2-cache-controller@48242000 {
    		compatible = "arm,pl310-cache";
    		reg = <0x48242000 0x1000>;
    		cache-unified;
    		cache-level = <0x2>;
    	};
    
    	ocp {
    		compatible = "ti,am4372-l3-noc", "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    		ti,hwmods = "l3_main";
    		reg = <0x44000000 0x400000 0x44800000 0x400000>;
    		interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
    		u-boot,dm-spl;
    
    		l4_wkup@44c00000 {
    			compatible = "ti,am4-l4-wkup", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x44c00000 0x287000>;
    			phandle = <0x42>;
    
    			prcm@1f0000 {
    				compatible = "ti,am4-prcm";
    				reg = <0x1f0000 0x11000>;
    				phandle = <0x43>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x44>;
    
    					clk_32768_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x13>;
    					};
    
    					clk_rc32k_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x12>;
    					};
    
    					virt_19200000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x124f800>;
    						phandle = <0x22>;
    					};
    
    					virt_24000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x16e3600>;
    						phandle = <0x23>;
    					};
    
    					virt_25000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x17d7840>;
    						phandle = <0x24>;
    					};
    
    					virt_26000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x25>;
    					};
    
    					tclkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x11>;
    					};
    
    					dpll_core_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-core-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2d20 0x2d24 0x2d2c>;
    						phandle = <0x5>;
    					};
    
    					dpll_core_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-x2-clock";
    						clocks = <0x5>;
    						phandle = <0x6>;
    					};
    
    					dpll_core_m4_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2d38>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0xd>;
    					};
    
    					dpll_core_m5_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2d3c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x16>;
    					};
    
    					dpll_core_m6_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x6>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2d40>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x45>;
    					};
    
    					dpll_mpu_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2d60 0x2d64 0x2d6c>;
    						phandle = <0x2>;
    					};
    
    					dpll_mpu_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2d70>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x46>;
    					};
    
    					dpll_ddr_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2da0 0x2da4 0x2dac>;
    						phandle = <0x7>;
    					};
    
    					dpll_ddr_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2db0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x47>;
    					};
    
    					dpll_disp_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2e20 0x2e24 0x2e2c>;
    						phandle = <0x8>;
    					};
    
    					dpll_disp_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e30>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						ti,set-rate-parent;
    						phandle = <0xf>;
    					};
    
    					dpll_per_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-j-type-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2de0 0x2de4 0x2dec>;
    						phandle = <0x9>;
    					};
    
    					dpll_per_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x9>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2df0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0xa>;
    					};
    
    					dpll_per_m2_div4_wkupdm_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x48>;
    					};
    
    					dpll_per_m2_div4_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x49>;
    					};
    
    					clk_24mhz {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x8>;
    						phandle = <0xb>;
    					};
    
    					clkdiv32k_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xb>;
    						clock-mult = <0x1>;
    						clock-div = <0x2dc>;
    						phandle = <0xc>;
    					};
    
    					clkdiv32k_ick {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0xc>;
    						ti,bit-shift = <0x8>;
    						reg = <0x2a38>;
    						phandle = <0x10>;
    					};
    
    					sysclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xd>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0xe>;
    					};
    
    					pruss_ocp_gclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xe 0xf>;
    						reg = <0x4248>;
    						phandle = <0x4a>;
    					};
    
    					clk_32k_tpm_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x14>;
    					};
    
    					timer1_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4 0x10 0x11 0x12 0x13 0x14>;
    						reg = <0x4200>;
    						phandle = <0x4b>;
    					};
    
    					timer2_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x4204>;
    						phandle = <0x4c>;
    					};
    
    					timer3_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x4208>;
    						phandle = <0x4d>;
    					};
    
    					timer4_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x420c>;
    						phandle = <0x4e>;
    					};
    
    					timer5_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x4210>;
    						phandle = <0x4f>;
    					};
    
    					timer6_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x4214>;
    						phandle = <0x50>;
    					};
    
    					timer7_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10>;
    						reg = <0x4218>;
    						phandle = <0x51>;
    					};
    
    					wdt1_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x12 0x10>;
    						reg = <0x422c>;
    						phandle = <0x52>;
    					};
    
    					l3_gclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xd>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x53>;
    					};
    
    					dpll_core_m4_div2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xe>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x15>;
    					};
    
    					l4hs_gclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xd>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x54>;
    					};
    
    					l3s_gclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x15>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x32>;
    					};
    
    					l4ls_gclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x15>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x26>;
    					};
    
    					cpsw_125mhz_gclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x16>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x2e>;
    					};
    
    					cpsw_cpts_rft_clk {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xe 0x16 0xf>;
    						reg = <0x4238>;
    						phandle = <0x2f>;
    					};
    
    					clk_32k_mosc_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x17>;
    					};
    
    					gpio0_dbclk_mux_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x12 0x13 0x10 0x17 0x14>;
    						reg = <0x4240>;
    						phandle = <0x18>;
    					};
    
    					gpio0_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x18>;
    						ti,bit-shift = <0x8>;
    						reg = <0x2b68>;
    						phandle = <0x55>;
    					};
    
    					gpio1_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8c78>;
    						phandle = <0x56>;
    					};
    
    					gpio2_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8c80>;
    						phandle = <0x57>;
    					};
    
    					gpio3_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8c88>;
    						phandle = <0x58>;
    					};
    
    					gpio4_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8c90>;
    						phandle = <0x59>;
    					};
    
    					gpio5_dbclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x10>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8c98>;
    						phandle = <0x5a>;
    					};
    
    					mmc_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x5b>;
    					};
    
    					gfx_fclk_clksel_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xe 0xa>;
    						ti,bit-shift = <0x1>;
    						reg = <0x423c>;
    						phandle = <0x19>;
    					};
    
    					gfx_fck_div_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						reg = <0x423c>;
    						ti,max-div = <0x2>;
    						phandle = <0x5c>;
    					};
    
    					disp_clk {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xf 0x16 0xa>;
    						reg = <0x4244>;
    						ti,set-rate-parent;
    						phandle = <0x3e>;
    					};
    
    					dpll_extdev_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-clock";
    						clocks = <0x4 0x4>;
    						reg = <0x2e60 0x2e64 0x2e6c>;
    						phandle = <0x1a>;
    					};
    
    					dpll_extdev_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e70>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x5d>;
    					};
    
    					mux_synctimer32k_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x13 0x14 0x10>;
    						reg = <0x4230>;
    						phandle = <0x1b>;
    					};
    
    					synctimer_32kclk {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x1b>;
    						ti,bit-shift = <0x8>;
    						reg = <0x2a30>;
    						phandle = <0x5e>;
    					};
    
    					timer8_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10 0x14>;
    						reg = <0x421c>;
    						phandle = <0x5f>;
    					};
    
    					timer9_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10 0x14>;
    						reg = <0x4220>;
    						phandle = <0x60>;
    					};
    
    					timer10_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10 0x14>;
    						reg = <0x4224>;
    						phandle = <0x61>;
    					};
    
    					timer11_fck {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x4 0x10 0x14>;
    						reg = <0x4228>;
    						phandle = <0x62>;
    					};
    
    					cpsw_50m_clkdiv {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x16>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1c>;
    					};
    
    					cpsw_5m_clkdiv {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1c>;
    						clock-mult = <0x1>;
    						clock-div = <0xa>;
    						phandle = <0x63>;
    					};
    
    					dpll_ddr_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,am3-dpll-x2-clock";
    						clocks = <0x7>;
    						phandle = <0x1d>;
    					};
    
    					dpll_ddr_m4_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1d>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2db8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x64>;
    					};
    
    					dpll_per_clkdcoldo {
    						#clock-cells = <0x0>;
    						compatible = "ti,fixed-factor-clock";
    						clocks = <0x9>;
    						ti,clock-mult = <0x1>;
    						ti,clock-div = <0x1>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e14>;
    						ti,invert-autoidle-bit;
    						phandle = <0x1f>;
    					};
    
    					dll_aging_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4>;
    						reg = <0x4250>;
    						ti,dividers = <0x8 0x10 0x20>;
    						phandle = <0x65>;
    					};
    
    					div_core_25m_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xe>;
    						clock-mult = <0x1>;
    						clock-div = <0x8>;
    						phandle = <0x66>;
    					};
    
    					func_12m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x10>;
    						phandle = <0x3d>;
    					};
    
    					vtp_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x4>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x67>;
    					};
    
    					usbphy_32khz_clkmux {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x13 0x14>;
    						reg = <0x4260>;
    						phandle = <0x1e>;
    					};
    
    					usb_phy0_always_on_clk32k {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x1e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x2a40>;
    						phandle = <0x34>;
    					};
    
    					usb_phy1_always_on_clk32k {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x1e>;
    						ti,bit-shift = <0x8>;
    						reg = <0x2a48>;
    						phandle = <0x37>;
    					};
    
    					usb_otg_ss0_refclk960m {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x1f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8a60>;
    						phandle = <0x35>;
    					};
    
    					usb_otg_ss1_refclk960m {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x1f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x8a68>;
    						phandle = <0x38>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x68>;
    				};
    			};
    
    			scm@210000 {
    				compatible = "ti,am4-scm", "simple-bus";
    				reg = <0x210000 0x4000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x210000 0x4000>;
    				phandle = <0x69>;
    
    				pinmux@800 {
    					compatible = "ti,am437-padconf", "pinctrl-single";
    					reg = <0x800 0x31c>;
    					#interrupt-cells = <0x1>;
    					interrupt-controller;
    					pinctrl-single,register-width = <0x20>;
    					pinctrl-single,function-mask = <0xffffffff>;
    					pinctrl-names = "default", "sleep";
    					phandle = <0x6a>;
    
    					i2c0_pins {
    						pinctrl-single,pins = <0x18c 0x50000 0x188 0x50000>;
    						phandle = <0x29>;
    					};
    
    					uart0_pins {
    						pinctrl-single,pins = <0x170 0x50000 0x174 0x10000>;
    						phandle = <0x27>;
    					};
    
    					boot_usb_ms_pins_default {
    						pinctrl-single,pins = <0x2c4 0x10000>;
    						phandle = <0x3c>;
    					};
    
    					lte_usb_pins_default {
    						pinctrl-single,pins = <0x2c0 0x10000>;
    						phandle = <0x3a>;
    					};
    
    					emmc_pins {
    						pinctrl-single,pins = <0x80 0x50002 0x84 0x50002 0x0 0x50001 0x4 0x50001 0x8 0x50001 0xc 0x50001 0x10 0x50001 0x14 0x50001 0x18 0x50001 0x1c 0x50001>;
    						phandle = <0x2b>;
    					};
    
    					gpio1_pins {
    						pinctrl-single,pins = <0x30 0x20007 0x34 0x20007 0x38 0x20007 0x3c 0x20007>;
    						phandle = <0x28>;
    					};
    				};
    
    				scm_conf@0 {
    					compatible = "syscon";
    					reg = <0x0 0x800>;
    					phandle = <0x30>;
    
    					clocks {
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    						phandle = <0x6b>;
    
    						sys_clkin_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0x20 0x21>;
    							ti,bit-shift = <0x1f>;
    							reg = <0x40>;
    							phandle = <0x4>;
    						};
    
    						crystal_freq_sel_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0x22 0x23 0x24 0x25>;
    							ti,bit-shift = <0x1d>;
    							reg = <0x40>;
    							phandle = <0x21>;
    						};
    
    						sysboot_freq_sel_ck@44e10040 {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0x22 0x23 0x24 0x25>;
    							ti,bit-shift = <0x16>;
    							reg = <0x40>;
    							phandle = <0x20>;
    						};
    
    						adc_tsc_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x31>;
    						};
    
    						dcan0_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x3f>;
    						};
    
    						dcan1_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x40>;
    						};
    
    						mcasp0_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x6c>;
    						};
    
    						mcasp1_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x6d>;
    						};
    
    						smartreflex0_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x6e>;
    						};
    
    						smartreflex1_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x6f>;
    						};
    
    						sha0_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x70>;
    						};
    
    						aes0_fck {
    							#clock-cells = <0x0>;
    							compatible = "fixed-factor-clock";
    							clocks = <0x4>;
    							clock-mult = <0x1>;
    							clock-div = <0x1>;
    							phandle = <0x71>;
    						};
    
    						ehrpwm0_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x0>;
    							reg = <0x664>;
    							phandle = <0x72>;
    						};
    
    						ehrpwm1_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x1>;
    							reg = <0x664>;
    							phandle = <0x73>;
    						};
    
    						ehrpwm2_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x2>;
    							reg = <0x664>;
    							phandle = <0x74>;
    						};
    
    						ehrpwm3_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x4>;
    							reg = <0x664>;
    							phandle = <0x75>;
    						};
    
    						ehrpwm4_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x5>;
    							reg = <0x664>;
    							phandle = <0x76>;
    						};
    
    						ehrpwm5_tbclk {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0x26>;
    							ti,bit-shift = <0x6>;
    							reg = <0x664>;
    							phandle = <0x77>;
    						};
    					};
    				};
    
    				clockdomains {
    					phandle = <0x78>;
    				};
    			};
    		};
    
    		emif@4c000000 {
    			compatible = "ti,emif-am4372";
    			reg = <0x4c000000 0x1000000>;
    			ti,hwmods = "emif";
    			phandle = <0x79>;
    		};
    
    		edma@49000000 {
    			compatible = "ti,edma3";
    			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
    			reg = <0x49000000 0x10000 0x44e10f90 0x10>;
    			interrupts = <0x0 0xc 0x4 0x0 0xd 0x4 0x0 0xe 0x4>;
    			#dma-cells = <0x1>;
    			phandle = <0x2a>;
    		};
    
    		serial@44e09000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x44e09000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x48 0x4>;
    			ti,hwmods = "uart1";
    			pinctrl-names = "default";
    			pinctrl-0 = <0x27>;
    			u-boot,dm-spl;
    			status = "okay";
    			phandle = <0x7a>;
    		};
    
    		serial@48022000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x48022000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x49 0x4>;
    			ti,hwmods = "uart2";
    			status = "disabled";
    			phandle = <0x7b>;
    		};
    
    		serial@48024000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x48024000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x4a 0x4>;
    			ti,hwmods = "uart3";
    			status = "disabled";
    			phandle = <0x7c>;
    		};
    
    		serial@481a6000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x481a6000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x2c 0x4>;
    			ti,hwmods = "uart4";
    			status = "disabled";
    			phandle = <0x7d>;
    		};
    
    		serial@481a8000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x481a8000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x2d 0x4>;
    			ti,hwmods = "uart5";
    			status = "disabled";
    			phandle = <0x7e>;
    		};
    
    		serial@481aa000 {
    			compatible = "ti,am4372-uart", "ti,omap2-uart";
    			reg = <0x481aa000 0x2000>;
    			reg-shift = <0x2>;
    			interrupts = <0x0 0x2e 0x4>;
    			ti,hwmods = "uart6";
    			status = "disabled";
    			phandle = <0x7f>;
    		};
    
    		mailbox@480C8000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x480c8000 0x200>;
    			interrupts = <0x0 0x4d 0x4>;
    			ti,hwmods = "mailbox";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0x8>;
    			phandle = <0x80>;
    
    			wkup_m3 {
    				ti,mbox-tx = <0x0 0x0 0x0>;
    				ti,mbox-rx = <0x0 0x0 0x3>;
    				phandle = <0x81>;
    			};
    		};
    
    		timer@44e31000 {
    			compatible = "ti,am4372-timer-1ms", "ti,am335x-timer-1ms";
    			reg = <0x44e31000 0x400>;
    			interrupts = <0x0 0x43 0x4>;
    			ti,timer-alwon;
    			ti,hwmods = "timer1";
    			phandle = <0x82>;
    		};
    
    		timer@48040000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48040000 0x400>;
    			interrupts = <0x0 0x44 0x4>;
    			ti,hwmods = "timer2";
    			phandle = <0x83>;
    		};
    
    		timer@48042000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48042000 0x400>;
    			interrupts = <0x0 0x45 0x4>;
    			ti,hwmods = "timer3";
    			status = "disabled";
    			phandle = <0x84>;
    		};
    
    		timer@48044000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48044000 0x400>;
    			interrupts = <0x0 0x5c 0x4>;
    			ti,timer-pwm;
    			ti,hwmods = "timer4";
    			status = "disabled";
    			phandle = <0x85>;
    		};
    
    		timer@48046000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48046000 0x400>;
    			interrupts = <0x0 0x5d 0x4>;
    			ti,timer-pwm;
    			ti,hwmods = "timer5";
    			status = "disabled";
    			phandle = <0x86>;
    		};
    
    		timer@48048000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48048000 0x400>;
    			interrupts = <0x0 0x5e 0x4>;
    			ti,timer-pwm;
    			ti,hwmods = "timer6";
    			status = "disabled";
    			phandle = <0x87>;
    		};
    
    		timer@4804a000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x4804a000 0x400>;
    			interrupts = <0x0 0x5f 0x4>;
    			ti,timer-pwm;
    			ti,hwmods = "timer7";
    			status = "disabled";
    			phandle = <0x88>;
    		};
    
    		timer@481c1000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x481c1000 0x400>;
    			interrupts = <0x0 0x83 0x4>;
    			ti,hwmods = "timer8";
    			status = "disabled";
    			phandle = <0x89>;
    		};
    
    		timer@4833d000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x4833d000 0x400>;
    			interrupts = <0x0 0x84 0x4>;
    			ti,hwmods = "timer9";
    			status = "disabled";
    			phandle = <0x8a>;
    		};
    
    		timer@4833f000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x4833f000 0x400>;
    			interrupts = <0x0 0x85 0x4>;
    			ti,hwmods = "timer10";
    			status = "disabled";
    			phandle = <0x8b>;
    		};
    
    		timer@48341000 {
    			compatible = "ti,am4372-timer", "ti,am335x-timer";
    			reg = <0x48341000 0x400>;
    			interrupts = <0x0 0x86 0x4>;
    			ti,hwmods = "timer11";
    			status = "disabled";
    			phandle = <0x8c>;
    		};
    
    		counter@44e86000 {
    			compatible = "ti,am4372-counter32k", "ti,omap-counter32k";
    			reg = <0x44e86000 0x40>;
    			ti,hwmods = "counter_32k";
    			phandle = <0x8d>;
    		};
    
    		rtc@44e3e000 {
    			compatible = "ti,am4372-rtc", "ti,da830-rtc";
    			reg = <0x44e3e000 0x1000>;
    			interrupts = <0x0 0x4b 0x4 0x0 0x4c 0x4>;
    			ti,hwmods = "rtc";
    			status = "disabled";
    			phandle = <0x8e>;
    		};
    
    		wdt@44e35000 {
    			compatible = "ti,am4372-wdt", "ti,omap3-wdt";
    			reg = <0x44e35000 0x1000>;
    			interrupts = <0x0 0x5b 0x4>;
    			ti,hwmods = "wd_timer2";
    			phandle = <0x8f>;
    		};
    
    		gpio@44e07000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x44e07000 0x1000>;
    			interrupts = <0x0 0x60 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio1";
    			status = "disabled";
    			phandle = <0x90>;
    		};
    
    		gpio@4804c000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x4804c000 0x1000>;
    			interrupts = <0x0 0x62 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio2";
    			status = "okay";
    			pinctrl-names = "default";
    			pinctrl-0 = <0x28>;
    			phandle = <0x2d>;
    		};
    
    		gpio@481ac000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x481ac000 0x1000>;
    			interrupts = <0x0 0x20 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio3";
    			status = "disabled";
    			phandle = <0x91>;
    		};
    
    		gpio@481ae000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x481ae000 0x1000>;
    			interrupts = <0x0 0x3e 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio4";
    			status = "disabled";
    			phandle = <0x92>;
    		};
    
    		gpio@48320000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x48320000 0x1000>;
    			interrupts = <0x0 0x6a 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio5";
    			status = "disabled";
    			phandle = <0x93>;
    		};
    
    		gpio@48322000 {
    			compatible = "ti,am4372-gpio", "ti,omap4-gpio";
    			reg = <0x48322000 0x1000>;
    			interrupts = <0x0 0x94 0x4>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,hwmods = "gpio6";
    			status = "disabled";
    			ti,no-reset-on-init;
    			phandle = <0x94>;
    		};
    
    		spinlock@480ca000 {
    			compatible = "ti,omap4-hwspinlock";
    			reg = <0x480ca000 0x1000>;
    			ti,hwmods = "spinlock";
    			#hwlock-cells = <0x1>;
    			phandle = <0x95>;
    		};
    
    		i2c@44e0b000 {
    			compatible = "ti,am4372-i2c", "ti,omap4-i2c";
    			reg = <0x44e0b000 0x1000>;
    			interrupts = <0x0 0x46 0x4>;
    			ti,hwmods = "i2c1";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "okay";
    			pinctrl-names = "default";
    			pinctrl-0 = <0x29>;
    			clock-frequency = <0x186a0>;
    			phandle = <0x96>;
    
    			tps65218@24 {
    				reg = <0x24>;
    				compatible = "ti,tps65218";
    				interrupts = <0x0 0x7 0x0>;
    				interrupt-controller;
    				#interrupt-cells = <0x2>;
    				phandle = <0x97>;
    
    				regulator-dcdc1 {
    					compatible = "ti,tps65218-dcdc1";
    					regulator-name = "vdd_core";
    					regulator-min-microvolt = <0xdea80>;
    					regulator-max-microvolt = <0x1174c0>;
    					regulator-boot-on;
    					regulator-always-on;
    					phandle = <0x98>;
    				};
    
    				regulator-dcdc2 {
    					compatible = "ti,tps65218-dcdc2";
    					regulator-name = "vdd_mpu";
    					regulator-min-microvolt = <0xdea80>;
    					regulator-max-microvolt = <0x1506d0>;
    					regulator-boot-on;
    					regulator-always-on;
    					phandle = <0x99>;
    				};
    
    				regulator-dcdc3 {
    					compatible = "ti,tps65218-dcdc3";
    					regulator-name = "vdcdc3";
    					regulator-min-microvolt = <0x16e360>;
    					regulator-max-microvolt = <0x16e360>;
    					regulator-boot-on;
    					regulator-always-on;
    					phandle = <0x9a>;
    				};
    
    				regulator-dcdc5 {
    					compatible = "ti,tps65218-dcdc5";
    					regulator-name = "v1_0bat";
    					regulator-min-microvolt = <0xf4240>;
    					regulator-max-microvolt = <0xf4240>;
    					phandle = <0x9b>;
    				};
    
    				regulator-dcdc6 {
    					compatible = "ti,tps65218-dcdc6";
    					regulator-name = "v1_8bat";
    					regulator-min-microvolt = <0x1b7740>;
    					regulator-max-microvolt = <0x1b7740>;
    					phandle = <0x9c>;
    				};
    
    				regulator-ldo1 {
    					compatible = "ti,tps65218-ldo1";
    					regulator-min-microvolt = <0x1b7740>;
    					regulator-max-microvolt = <0x1b7740>;
    					regulator-boot-on;
    					regulator-always-on;
    					phandle = <0x9d>;
    				};
    			};
    		};
    
    		i2c@4802a000 {
    			compatible = "ti,am4372-i2c", "ti,omap4-i2c";
    			reg = <0x4802a000 0x1000>;
    			interrupts = <0x0 0x47 0x4>;
    			ti,hwmods = "i2c2";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0x9e>;
    		};
    
    		i2c@4819c000 {
    			compatible = "ti,am4372-i2c", "ti,omap4-i2c";
    			reg = <0x4819c000 0x1000>;
    			interrupts = <0x0 0x1e 0x4>;
    			ti,hwmods = "i2c3";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0x9f>;
    		};
    
    		spi@48030000 {
    			compatible = "ti,am4372-mcspi", "ti,omap4-mcspi";
    			reg = <0x48030000 0x400>;
    			interrupts = <0x0 0x41 0x4>;
    			ti,hwmods = "spi0";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0xa0>;
    		};
    
    		mmc@48060000 {
    			compatible = "ti,omap4-hsmmc";
    			reg = <0x48060000 0x1000>;
    			ti,hwmods = "mmc1";
    			ti,dual-volt;
    			ti,needs-special-reset;
    			dmas = <0x2a 0x18 0x2a 0x19>;
    			dma-names = "tx", "rx";
    			interrupts = <0x0 0x40 0x4>;
    			status = "disabled";
    			phandle = <0xa1>;
    		};
    
    		mmc@481d8000 {
    			compatible = "ti,omap4-hsmmc";
    			reg = <0x481d8000 0x1000>;
    			ti,hwmods = "mmc2";
    			ti,needs-special-reset;
    			dmas = <0x2a 0x2 0x2a 0x3>;
    			dma-names = "tx", "rx";
    			interrupts = <0x0 0x1c 0x4>;
    			status = "okay";
    			pinctrl-names = "default";
    			pinctrl-0 = <0x2b>;
    			vmmc-supply = <0x2c>;
    			vqmmc-supply = <0x2c>;
    			bus-width = <0x8>;
    			ti,non-removable;
    			max-frequency = <0x18cba80>;
    			no-1-8-v;
    			reset-gpios = <0x2d 0xd 0x0>;
    			phandle = <0xa2>;
    		};
    
    		mmc@47810000 {
    			compatible = "ti,omap4-hsmmc";
    			reg = <0x47810000 0x1000>;
    			ti,hwmods = "mmc3";
    			ti,needs-special-reset;
    			interrupts = <0x0 0x1d 0x4>;
    			status = "disabled";
    			phandle = <0xa3>;
    		};
    
    		spi@481a0000 {
    			compatible = "ti,am4372-mcspi", "ti,omap4-mcspi";
    			reg = <0x481a0000 0x400>;
    			interrupts = <0x0 0x7d 0x4>;
    			ti,hwmods = "spi1";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0xa4>;
    		};
    
    		spi@481a2000 {
    			compatible = "ti,am4372-mcspi", "ti,omap4-mcspi";
    			reg = <0x481a2000 0x400>;
    			interrupts = <0x0 0x7e 0x4>;
    			ti,hwmods = "spi2";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0xa5>;
    		};
    
    		spi@481a4000 {
    			compatible = "ti,am4372-mcspi", "ti,omap4-mcspi";
    			reg = <0x481a4000 0x400>;
    			interrupts = <0x0 0x88 0x4>;
    			ti,hwmods = "spi3";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0xa6>;
    		};
    
    		spi@48345000 {
    			compatible = "ti,am4372-mcspi", "ti,omap4-mcspi";
    			reg = <0x48345000 0x400>;
    			interrupts = <0x0 0x89 0x4>;
    			ti,hwmods = "spi4";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0xa7>;
    		};
    
    		ethernet@4a100000 {
    			compatible = "ti,am4372-cpsw", "ti,cpsw";
    			reg = <0x4a100000 0x800 0x4a101200 0x100>;
    			interrupts = <0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ti,hwmods = "cpgmac0";
    			clocks = <0x2e 0x2f>;
    			clock-names = "fck", "cpts";
    			status = "disabled";
    			cpdma_channels = <0x8>;
    			ale_entries = <0x400>;
    			bd_ram_size = <0x2000>;
    			no_bd_ram = <0x0>;
    			rx_descs = <0x40>;
    			mac_control = <0x20>;
    			slaves = <0x2>;
    			active_slave = <0x0>;
    			cpts_clock_mult = <0x80000000>;
    			cpts_clock_shift = <0x1d>;
    			syscon = <0x30>;
    			ranges;
    			phandle = <0xa8>;
    
    			mdio@4a101000 {
    				compatible = "ti,am4372-mdio", "ti,davinci_mdio";
    				reg = <0x4a101000 0x100>;
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				ti,hwmods = "davinci_mdio";
    				bus_freq = <0xf4240>;
    				status = "disabled";
    				phandle = <0xa9>;
    			};
    
    			slave@4a100200 {
    				mac-address = [00 00 00 00 00 00];
    				phandle = <0xaa>;
    			};
    
    			slave@4a100300 {
    				mac-address = [00 00 00 00 00 00];
    				phandle = <0xab>;
    			};
    
    			cpsw-phy-sel@44e10650 {
    				compatible = "ti,am43xx-cpsw-phy-sel";
    				reg = <0x44e10650 0x4>;
    				reg-names = "gmii-sel";
    				phandle = <0xac>;
    			};
    		};
    
    		epwmss@48300000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48300000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss0";
    			status = "disabled";
    			phandle = <0xad>;
    
    			ecap@48300100 {
    				compatible = "ti,am4372-ecap", "ti,am33xx-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48300100 0x80>;
    				ti,hwmods = "ecap0";
    				status = "disabled";
    				phandle = <0xae>;
    			};
    
    			ehrpwm@48300200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48300200 0x80>;
    				ti,hwmods = "ehrpwm0";
    				status = "disabled";
    				phandle = <0xaf>;
    			};
    		};
    
    		epwmss@48302000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48302000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss1";
    			status = "disabled";
    			phandle = <0xb0>;
    
    			ecap@48302100 {
    				compatible = "ti,am4372-ecap", "ti,am33xx-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48302100 0x80>;
    				ti,hwmods = "ecap1";
    				status = "disabled";
    				phandle = <0xb1>;
    			};
    
    			ehrpwm@48302200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48302200 0x80>;
    				ti,hwmods = "ehrpwm1";
    				status = "disabled";
    				phandle = <0xb2>;
    			};
    		};
    
    		epwmss@48304000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48304000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss2";
    			status = "disabled";
    			phandle = <0xb3>;
    
    			ecap@48304100 {
    				compatible = "ti,am4372-ecap", "ti,am33xx-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48304100 0x80>;
    				ti,hwmods = "ecap2";
    				status = "disabled";
    				phandle = <0xb4>;
    			};
    
    			ehrpwm@48304200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48304200 0x80>;
    				ti,hwmods = "ehrpwm2";
    				status = "disabled";
    				phandle = <0xb5>;
    			};
    		};
    
    		epwmss@48306000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48306000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss3";
    			status = "disabled";
    			phandle = <0xb6>;
    
    			ehrpwm@48306200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48306200 0x80>;
    				ti,hwmods = "ehrpwm3";
    				status = "disabled";
    				phandle = <0xb7>;
    			};
    		};
    
    		epwmss@48308000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48308000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss4";
    			status = "disabled";
    			phandle = <0xb8>;
    
    			ehrpwm@48308200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48308200 0x80>;
    				ti,hwmods = "ehrpwm4";
    				status = "disabled";
    				phandle = <0xb9>;
    			};
    		};
    
    		epwmss@4830a000 {
    			compatible = "ti,am4372-pwmss", "ti,am33xx-pwmss";
    			reg = <0x4830a000 0x10>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "epwmss5";
    			status = "disabled";
    			phandle = <0xba>;
    
    			ehrpwm@4830a200 {
    				compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x4830a200 0x80>;
    				ti,hwmods = "ehrpwm5";
    				status = "disabled";
    				phandle = <0xbb>;
    			};
    		};
    
    		tscadc@44e0d000 {
    			compatible = "ti,am3359-tscadc";
    			reg = <0x44e0d000 0x1000>;
    			ti,hwmods = "adc_tsc";
    			interrupts = <0x0 0x10 0x4>;
    			clocks = <0x31>;
    			clock-names = "fck";
    			status = "disabled";
    			phandle = <0xbc>;
    
    			tsc {
    				compatible = "ti,am3359-tsc";
    			};
    
    			adc {
    				#io-channel-cells = <0x1>;
    				compatible = "ti,am3359-adc";
    			};
    		};
    
    		sham@53100000 {
    			compatible = "ti,omap5-sham";
    			ti,hwmods = "sham";
    			reg = <0x53100000 0x300>;
    			dmas = <0x2a 0x24>;
    			dma-names = "rx";
    			interrupts = <0x0 0x6d 0x4>;
    			phandle = <0xbd>;
    		};
    
    		aes@53501000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes";
    			reg = <0x53501000 0xa0>;
    			interrupts = <0x0 0x67 0x4>;
    			dmas = <0x2a 0x6 0x2a 0x5>;
    			dma-names = "tx", "rx";
    			phandle = <0xbe>;
    		};
    
    		des@53701000 {
    			compatible = "ti,omap4-des";
    			ti,hwmods = "des";
    			reg = <0x53701000 0xa0>;
    			interrupts = <0x0 0x82 0x4>;
    			dmas = <0x2a 0x22 0x2a 0x21>;
    			dma-names = "tx", "rx";
    			phandle = <0xbf>;
    		};
    
    		mcasp@48038000 {
    			compatible = "ti,am33xx-mcasp-audio";
    			ti,hwmods = "mcasp0";
    			reg = <0x48038000 0x2000 0x46000000 0x400000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x50 0x4 0x0 0x51 0x4>;
    			interrupt-names = "tx", "rx";
    			status = "disabled";
    			dmas = <0x2a 0x8 0x2a 0x9>;
    			dma-names = "tx", "rx";
    			phandle = <0xc0>;
    		};
    
    		mcasp@4803C000 {
    			compatible = "ti,am33xx-mcasp-audio";
    			ti,hwmods = "mcasp1";
    			reg = <0x4803c000 0x2000 0x46400000 0x400000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x52 0x4 0x0 0x53 0x4>;
    			interrupt-names = "tx", "rx";
    			status = "disabled";
    			dmas = <0x2a 0xa 0x2a 0xb>;
    			dma-names = "tx", "rx";
    			phandle = <0xc1>;
    		};
    
    		elm@48080000 {
    			compatible = "ti,am3352-elm";
    			reg = <0x48080000 0x2000>;
    			interrupts = <0x0 0x4 0x4>;
    			ti,hwmods = "elm";
    			clocks = <0x26>;
    			clock-names = "fck";
    			status = "disabled";
    			phandle = <0xc2>;
    		};
    
    		gpmc@50000000 {
    			compatible = "ti,am3352-gpmc";
    			ti,hwmods = "gpmc";
    			clocks = <0x32>;
    			clock-names = "fck";
    			reg = <0x50000000 0x2000>;
    			interrupts = <0x0 0x64 0x4>;
    			gpmc,num-cs = <0x7>;
    			gpmc,num-waitpins = <0x2>;
    			#address-cells = <0x2>;
    			#size-cells = <0x1>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			status = "disabled";
    			phandle = <0xc3>;
    		};
    
    		control-phy@44e10620 {
    			compatible = "ti,control-phy-usb2-am437";
    			reg = <0x44e10620 0x4>;
    			reg-names = "power";
    			phandle = <0x33>;
    		};
    
    		control-phy@0x44e10628 {
    			compatible = "ti,control-phy-usb2-am437";
    			reg = <0x44e10628 0x4>;
    			reg-names = "power";
    			phandle = <0x36>;
    		};
    
    		ocp2scp@483a8000 {
    			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "ocp2scp0";
    			phandle = <0xc4>;
    
    			phy@483a8000 {
    				compatible = "ti,am437x-usb2";
    				reg = <0x483a8000 0x8000>;
    				ctrl-module = <0x33>;
    				clocks = <0x34 0x35>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				status = "okay";
    				phandle = <0x39>;
    			};
    		};
    
    		ocp2scp@483e8000 {
    			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			ti,hwmods = "ocp2scp1";
    			phandle = <0xc5>;
    
    			phy@483e8000 {
    				compatible = "ti,am437x-usb2";
    				reg = <0x483e8000 0x8000>;
    				ctrl-module = <0x36>;
    				clocks = <0x37 0x38>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				status = "okay";
    				phandle = <0x3b>;
    			};
    		};
    
    		omap_dwc3@48380000 {
    			compatible = "ti,am437x-dwc3";
    			ti,hwmods = "usb_otg_ss0";
    			reg = <0x48380000 0x10000>;
    			interrupts = <0x0 0xac 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x1>;
    			ranges;
    			phandle = <0xc6>;
    
    			usb@48390000 {
    				compatible = "synopsys,dwc3";
    				reg = <0x48390000 0x10000>;
    				interrupts = <0x0 0xa8 0x4>;
    				phys = <0x39>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "peripheral";
    				status = "okay";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				pinctrl-names = "default";
    				pinctrl-0 = <0x3a>;
    				phandle = <0xc7>;
    			};
    		};
    
    		omap_dwc3@483c0000 {
    			compatible = "ti,am437x-dwc3";
    			ti,hwmods = "usb_otg_ss1";
    			reg = <0x483c0000 0x10000>;
    			interrupts = <0x0 0xb2 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x1>;
    			ranges;
    			phandle = <0xc8>;
    
    			usb@483d0000 {
    				compatible = "synopsys,dwc3";
    				reg = <0x483d0000 0x10000>;
    				interrupts = <0x0 0xae 0x4>;
    				phys = <0x3b>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "host";
    				status = "okay";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				pinctrl-names = "default";
    				pinctrl-0 = <0x3c>;
    				phandle = <0xc9>;
    			};
    		};
    
    		qspi@47900000 {
    			compatible = "ti,am4372-qspi";
    			reg = <0x47900000 0x100 0x30000000 0x4000000>;
    			reg-names = "qspi_base", "qspi_mmap";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "qspi";
    			interrupts = <0x0 0x8a 0x4>;
    			num-cs = <0x4>;
    			status = "disabled";
    			phandle = <0xca>;
    		};
    
    		hdq@48347000 {
    			compatible = "ti,am4372-hdq";
    			reg = <0x48347000 0x1000>;
    			interrupts = <0x0 0x8b 0x4>;
    			clocks = <0x3d>;
    			clock-names = "fck";
    			ti,hwmods = "hdq1w";
    			status = "disabled";
    			phandle = <0xcb>;
    		};
    
    		dss@4832a000 {
    			compatible = "ti,omap3-dss";
    			reg = <0x4832a000 0x200>;
    			status = "disabled";
    			ti,hwmods = "dss_core";
    			clocks = <0x3e>;
    			clock-names = "fck";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			phandle = <0xcc>;
    
    			dispc@4832a400 {
    				compatible = "ti,omap3-dispc";
    				reg = <0x4832a400 0x400>;
    				interrupts = <0x0 0x7f 0x4>;
    				ti,hwmods = "dss_dispc";
    				clocks = <0x3e>;
    				clock-names = "fck";
    				phandle = <0xcd>;
    			};
    
    			rfbi@4832a800 {
    				compatible = "ti,omap3-rfbi";
    				reg = <0x4832a800 0x100>;
    				ti,hwmods = "dss_rfbi";
    				clocks = <0x3e>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0xce>;
    			};
    		};
    
    		ocmcram@40300000 {
    			compatible = "mmio-sram";
    			reg = <0x40300000 0x40000>;
    			phandle = <0xcf>;
    		};
    
    		can@481cc000 {
    			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
    			ti,hwmods = "d_can0";
    			clocks = <0x3f>;
    			clock-names = "fck";
    			reg = <0x481cc000 0x2000>;
    			syscon-raminit = <0x30 0x644 0x0>;
    			interrupts = <0x0 0x34 0x4>;
    			status = "disabled";
    			phandle = <0xd0>;
    		};
    
    		can@481d0000 {
    			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
    			ti,hwmods = "d_can1";
    			clocks = <0x40>;
    			clock-names = "fck";
    			reg = <0x481d0000 0x2000>;
    			syscon-raminit = <0x30 0x644 0x1>;
    			interrupts = <0x0 0x31 0x4>;
    			status = "disabled";
    			phandle = <0xd1>;
    		};
    
    		vpfe@48326000 {
    			compatible = "ti,am437x-vpfe";
    			reg = <0x48326000 0x2000>;
    			interrupts = <0x0 0x30 0x4>;
    			ti,hwmods = "vpfe0";
    			status = "disabled";
    			phandle = <0xd2>;
    		};
    
    		vpfe@48328000 {
    			compatible = "ti,am437x-vpfe";
    			reg = <0x48328000 0x2000>;
    			interrupts = <0x0 0x32 0x4>;
    			ti,hwmods = "vpfe1";
    			status = "disabled";
    			phandle = <0xd3>;
    		};
    	};
    
    	fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcsd_fixed";
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		enable-active-high;
    		phandle = <0x2c>;
    	};
    
    	__symbols__ {
    		cpu = "/cpus/cpu@0";
    		gic = "/interrupt-controller@48241000";
    		wakeupgen = "/interrupt-controller@48281000";
    		l4_wkup = "/ocp/l4_wkup@44c00000";
    		prcm = "/ocp/l4_wkup@44c00000/prcm@1f0000";
    		prcm_clocks = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks";
    		clk_32768_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clk_32768_ck";
    		clk_rc32k_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clk_rc32k_ck";
    		virt_19200000_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/virt_19200000_ck";
    		virt_24000000_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/virt_24000000_ck";
    		virt_25000000_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/virt_25000000_ck";
    		virt_26000000_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/virt_26000000_ck";
    		tclkin_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/tclkin_ck";
    		dpll_core_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_ck";
    		dpll_core_x2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_x2_ck";
    		dpll_core_m4_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_m4_ck";
    		dpll_core_m5_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_m5_ck";
    		dpll_core_m6_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_m6_ck";
    		dpll_mpu_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_mpu_ck";
    		dpll_mpu_m2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_mpu_m2_ck";
    		dpll_ddr_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_ddr_ck";
    		dpll_ddr_m2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_ddr_m2_ck";
    		dpll_disp_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_disp_ck";
    		dpll_disp_m2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_disp_m2_ck";
    		dpll_per_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_per_ck";
    		dpll_per_m2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_per_m2_ck";
    		dpll_per_m2_div4_wkupdm_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_per_m2_div4_wkupdm_ck";
    		dpll_per_m2_div4_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_per_m2_div4_ck";
    		clk_24mhz = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clk_24mhz";
    		clkdiv32k_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clkdiv32k_ck";
    		clkdiv32k_ick = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clkdiv32k_ick";
    		sysclk_div = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/sysclk_div";
    		pruss_ocp_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/pruss_ocp_gclk";
    		clk_32k_tpm_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clk_32k_tpm_ck";
    		timer1_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer1_fck";
    		timer2_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer2_fck";
    		timer3_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer3_fck";
    		timer4_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer4_fck";
    		timer5_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer5_fck";
    		timer6_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer6_fck";
    		timer7_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer7_fck";
    		wdt1_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/wdt1_fck";
    		l3_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/l3_gclk";
    		dpll_core_m4_div2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_core_m4_div2_ck";
    		l4hs_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/l4hs_gclk";
    		l3s_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/l3s_gclk";
    		l4ls_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/l4ls_gclk";
    		cpsw_125mhz_gclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/cpsw_125mhz_gclk";
    		cpsw_cpts_rft_clk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/cpsw_cpts_rft_clk";
    		clk_32k_mosc_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/clk_32k_mosc_ck";
    		gpio0_dbclk_mux_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio0_dbclk_mux_ck";
    		gpio0_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio0_dbclk";
    		gpio1_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio1_dbclk";
    		gpio2_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio2_dbclk";
    		gpio3_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio3_dbclk";
    		gpio4_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio4_dbclk";
    		gpio5_dbclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gpio5_dbclk";
    		mmc_clk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/mmc_clk";
    		gfx_fclk_clksel_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gfx_fclk_clksel_ck";
    		gfx_fck_div_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/gfx_fck_div_ck";
    		disp_clk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/disp_clk";
    		dpll_extdev_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_extdev_ck";
    		dpll_extdev_m2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_extdev_m2_ck";
    		mux_synctimer32k_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/mux_synctimer32k_ck";
    		synctimer_32kclk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/synctimer_32kclk";
    		timer8_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer8_fck";
    		timer9_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer9_fck";
    		timer10_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer10_fck";
    		timer11_fck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/timer11_fck";
    		cpsw_50m_clkdiv = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/cpsw_50m_clkdiv";
    		cpsw_5m_clkdiv = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/cpsw_5m_clkdiv";
    		dpll_ddr_x2_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_ddr_x2_ck";
    		dpll_ddr_m4_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_ddr_m4_ck";
    		dpll_per_clkdcoldo = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dpll_per_clkdcoldo";
    		dll_aging_clk_div = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/dll_aging_clk_div";
    		div_core_25m_ck = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/div_core_25m_ck";
    		func_12m_clk = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/func_12m_clk";
    		vtp_clk_div = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/vtp_clk_div";
    		usbphy_32khz_clkmux = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/usbphy_32khz_clkmux";
    		usb_phy0_always_on_clk32k = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/usb_phy0_always_on_clk32k";
    		usb_phy1_always_on_clk32k = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/usb_phy1_always_on_clk32k";
    		usb_otg_ss0_refclk960m = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/usb_otg_ss0_refclk960m";
    		usb_otg_ss1_refclk960m = "/ocp/l4_wkup@44c00000/prcm@1f0000/clocks/usb_otg_ss1_refclk960m";
    		prcm_clockdomains = "/ocp/l4_wkup@44c00000/prcm@1f0000/clockdomains";
    		scm = "/ocp/l4_wkup@44c00000/scm@210000";
    		am43xx_pinmux = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800";
    		i2c0_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/i2c0_pins";
    		uart0_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/uart0_pins";
    		boot_usb_ms_pins_default = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/boot_usb_ms_pins_default";
    		lte_usb_pins_default = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/lte_usb_pins_default";
    		emmc_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/emmc_pins";
    		gpio1_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/gpio1_pins";
    		scm_conf = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0";
    		scm_clocks = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks";
    		sys_clkin_ck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/sys_clkin_ck";
    		crystal_freq_sel_ck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/crystal_freq_sel_ck";
    		sysboot_freq_sel_ck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/sysboot_freq_sel_ck@44e10040";
    		adc_tsc_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/adc_tsc_fck";
    		dcan0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/dcan0_fck";
    		dcan1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/dcan1_fck";
    		mcasp0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/mcasp0_fck";
    		mcasp1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/mcasp1_fck";
    		smartreflex0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/smartreflex0_fck";
    		smartreflex1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/smartreflex1_fck";
    		sha0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/sha0_fck";
    		aes0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/aes0_fck";
    		ehrpwm0_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm0_tbclk";
    		ehrpwm1_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm1_tbclk";
    		ehrpwm2_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm2_tbclk";
    		ehrpwm3_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm3_tbclk";
    		ehrpwm4_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm4_tbclk";
    		ehrpwm5_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm5_tbclk";
    		scm_clockdomains = "/ocp/l4_wkup@44c00000/scm@210000/clockdomains";
    		emif = "/ocp/emif@4c000000";
    		edma = "/ocp/edma@49000000";
    		uart0 = "/ocp/serial@44e09000";
    		uart1 = "/ocp/serial@48022000";
    		uart2 = "/ocp/serial@48024000";
    		uart3 = "/ocp/serial@481a6000";
    		uart4 = "/ocp/serial@481a8000";
    		uart5 = "/ocp/serial@481aa000";
    		mailbox = "/ocp/mailbox@480C8000";
    		mbox_wkupm3 = "/ocp/mailbox@480C8000/wkup_m3";
    		timer1 = "/ocp/timer@44e31000";
    		timer2 = "/ocp/timer@48040000";
    		timer3 = "/ocp/timer@48042000";
    		timer4 = "/ocp/timer@48044000";
    		timer5 = "/ocp/timer@48046000";
    		timer6 = "/ocp/timer@48048000";
    		timer7 = "/ocp/timer@4804a000";
    		timer8 = "/ocp/timer@481c1000";
    		timer9 = "/ocp/timer@4833d000";
    		timer10 = "/ocp/timer@4833f000";
    		timer11 = "/ocp/timer@48341000";
    		counter32k = "/ocp/counter@44e86000";
    		rtc = "/ocp/rtc@44e3e000";
    		wdt = "/ocp/wdt@44e35000";
    		gpio0 = "/ocp/gpio@44e07000";
    		gpio1 = "/ocp/gpio@4804c000";
    		gpio2 = "/ocp/gpio@481ac000";
    		gpio3 = "/ocp/gpio@481ae000";
    		gpio4 = "/ocp/gpio@48320000";
    		gpio5 = "/ocp/gpio@48322000";
    		hwspinlock = "/ocp/spinlock@480ca000";
    		i2c0 = "/ocp/i2c@44e0b000";
    		tps65218 = "/ocp/i2c@44e0b000/tps65218@24";
    		dcdc1 = "/ocp/i2c@44e0b000/tps65218@24/regulator-dcdc1";
    		dcdc2 = "/ocp/i2c@44e0b000/tps65218@24/regulator-dcdc2";
    		dcdc3 = "/ocp/i2c@44e0b000/tps65218@24/regulator-dcdc3";
    		dcdc5 = "/ocp/i2c@44e0b000/tps65218@24/regulator-dcdc5";
    		dcdc6 = "/ocp/i2c@44e0b000/tps65218@24/regulator-dcdc6";
    		ldo1 = "/ocp/i2c@44e0b000/tps65218@24/regulator-ldo1";
    		i2c1 = "/ocp/i2c@4802a000";
    		i2c2 = "/ocp/i2c@4819c000";
    		spi0 = "/ocp/spi@48030000";
    		mmc1 = "/ocp/mmc@48060000";
    		mmc2 = "/ocp/mmc@481d8000";
    		mmc3 = "/ocp/mmc@47810000";
    		spi1 = "/ocp/spi@481a0000";
    		spi2 = "/ocp/spi@481a2000";
    		spi3 = "/ocp/spi@481a4000";
    		spi4 = "/ocp/spi@48345000";
    		mac = "/ocp/ethernet@4a100000";
    		davinci_mdio = "/ocp/ethernet@4a100000/mdio@4a101000";
    		cpsw_emac0 = "/ocp/ethernet@4a100000/slave@4a100200";
    		cpsw_emac1 = "/ocp/ethernet@4a100000/slave@4a100300";
    		phy_sel = "/ocp/ethernet@4a100000/cpsw-phy-sel@44e10650";
    		epwmss0 = "/ocp/epwmss@48300000";
    		ecap0 = "/ocp/epwmss@48300000/ecap@48300100";
    		ehrpwm0 = "/ocp/epwmss@48300000/ehrpwm@48300200";
    		epwmss1 = "/ocp/epwmss@48302000";
    		ecap1 = "/ocp/epwmss@48302000/ecap@48302100";
    		ehrpwm1 = "/ocp/epwmss@48302000/ehrpwm@48302200";
    		epwmss2 = "/ocp/epwmss@48304000";
    		ecap2 = "/ocp/epwmss@48304000/ecap@48304100";
    		ehrpwm2 = "/ocp/epwmss@48304000/ehrpwm@48304200";
    		epwmss3 = "/ocp/epwmss@48306000";
    		ehrpwm3 = "/ocp/epwmss@48306000/ehrpwm@48306200";
    		epwmss4 = "/ocp/epwmss@48308000";
    		ehrpwm4 = "/ocp/epwmss@48308000/ehrpwm@48308200";
    		epwmss5 = "/ocp/epwmss@4830a000";
    		ehrpwm5 = "/ocp/epwmss@4830a000/ehrpwm@4830a200";
    		tscadc = "/ocp/tscadc@44e0d000";
    		sham = "/ocp/sham@53100000";
    		aes = "/ocp/aes@53501000";
    		des = "/ocp/des@53701000";
    		mcasp0 = "/ocp/mcasp@48038000";
    		mcasp1 = "/ocp/mcasp@4803C000";
    		elm = "/ocp/elm@48080000";
    		gpmc = "/ocp/gpmc@50000000";
    		am43xx_control_usb2phy1 = "/ocp/control-phy@44e10620";
    		am43xx_control_usb2phy2 = "/ocp/control-phy@0x44e10628";
    		ocp2scp0 = "/ocp/ocp2scp@483a8000";
    		usb2_phy1 = "/ocp/ocp2scp@483a8000/phy@483a8000";
    		ocp2scp1 = "/ocp/ocp2scp@483e8000";
    		usb2_phy2 = "/ocp/ocp2scp@483e8000/phy@483e8000";
    		dwc3_1 = "/ocp/omap_dwc3@48380000";
    		usb1 = "/ocp/omap_dwc3@48380000/usb@48390000";
    		dwc3_2 = "/ocp/omap_dwc3@483c0000";
    		usb2 = "/ocp/omap_dwc3@483c0000/usb@483d0000";
    		qspi = "/ocp/qspi@47900000";
    		hdq = "/ocp/hdq@48347000";
    		dss = "/ocp/dss@4832a000";
    		dispc = "/ocp/dss@4832a000/dispc@4832a400";
    		rfbi = "/ocp/dss@4832a000/rfbi@4832a800";
    		ocmcram = "/ocp/ocmcram@40300000";
    		dcan0 = "/ocp/can@481cc000";
    		dcan1 = "/ocp/can@481d0000";
    		vpfe0 = "/ocp/vpfe@48326000";
    		vpfe1 = "/ocp/vpfe@48328000";
    		vmmcsd_fixed = "/fixedregulator-sd";
    	};
    };
    

  • Kamil,

    If you run your uboot build on the SK EVM, does the same error happen?

    Kamil Muza1 said:
    Why exactly is it saying PHY0 and USB0 while showing the addresses of the ocp2scp and phy of USB1? 

    This message is printed from the USB core layer, which always uses the index from 0. The core layer doesn't know how many usb controllers the platform has.

    Kamil Muza1 said:
    Do you recognize this type of error? err=-19?

    Error -19 is ENODEV, you can find it in include/linux/errno.h.

    Kamil Muza1 said:
    Please see attached my defconfig and dtb

    Please don't copy & paste the whole files. It has thousands of lines, Nobody can tell if there is any line wrong by just reviewing it in the thread, and it is too long in the thread, which makes reviewing the thread much more difficult. We all have the code base in the Processor SDK release, please just describe what you have changed, and only provide the patches for review.

    Kamil Muza1 said:
    Is there any other step that needs to be performed to bring USB up in uboot other than adding the correct DTS settings?

    Since your USB use case is exactly the same as that on the SK EVM - USB0 is in peripheral mode and USB1 is in host mode, so you basically can just take the SK EVM dts as is and don't need to change anything which are related to USB.