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Not able to communicate with Eth PHYs connected in CPSW9

Jeyaseelan Kirubaharan
Intellectual 775 points

Hi All,

We have a custom board where 2 PHYS are connected through RGMII and another 2 are connected through SGMII (In SGMII ,one is PHY and another ext switch) .Have attached the snapshot of schematics of how the external PHYs are connected .To start with we are configuring the 2 RGMII PHYs which are connected through RGMII5 /RGMII6 pins respectively. These two, we think  are connected to internal MAC ports of port no 5 and 6 respectively. So in the switch application software(mcu2_0) we have configured these  ports  as RGMII in main_tirtos.c assume this will override the default configuration of EVM board.

static const Cpsw_MacPort gCpswMainAppMacPorts[] =
{
CPSW_MAC_PORT_0,
#if defined(SOC_J721E)
CPSW_MAC_PORT_5, /* RGMII */
CPSW_MAC_PORT_6, /* RGMII */
CPSW_MAC_PORT_7, /* SGMII */

#endif
};

Also done the necessary changes in the source files in psdk  (board_ethernet_config.c, cpsw_appboardutils_j721e_evm.c) patches to them is added as an attachment. But when running the mcu2_0 with these changes , getting the below errors. 

CPSW_9G Test on MAIN NAVSS

Remote demo device (core : mcu2_0) .....

Cps

U-Boot SPL 2019.01-g350f3927b8 (Oct 18 2020 - 19:56:10 +0000)

w_openPorReading on-board EEPROM at 0x50 failed 1

tLink: Invalid Trying to boot from MMC2

SGMII/QSGMII port 5 configuration: -6

Cpsw_ioctlInternal: failed to open port 5 link: -ti_sci_power_domain_on: get_device

6

CpswMcm_enablePorts() failed to open MAC port: -6

Cpsw_openPortLink: Invalid SGMII/QSGMII

 

U-Boot 2019.01-g350f3927b8 (Oct 18 2020 - 19:56:10 +0000)

 

SoC:   J721E PG 1.0

Model: Texas Instruments K3 J721E SoC

port 6 cReading on-board EEPROM at 0x50 failed 1

Board: J721EX-PM1-SOM rev E2

DRAM:  o4 GiB

nfiguration: -6

CpsFlash: 0 Bytes

MMC:   w_iosdhci@4f80000: 0, sdhci@4fb0000: 1

Loading Environment from SPI Flash... ti_sci_power_domain_on: get_device(103) faile

ctlInternal: failed to open port 6 link: -6

CpswMcm_enablePorts() failed to open MAC port: -6

PHY 0 is alive

Please find the attached patches done for the configuration and let us know if anything is missed.PHYs_config.zip

With regards,

Jeyaseelan

  • 0
    Intellectual 775 points

    Hi All,

    We could see the PHYs are binded to the driver sucessfully in Port No : 4 & Port No : 5 using the remote_switch_firmware software. But we see the below error traces print continuously . Can you let us know what could be the cause of the same.

    CpswMcm_enableTrying to boot from MMC2
    Ports() Successfully opened MAC port: 0 - 0
    CpswMcm_enablePorts() ****Opening MAC Portti_sci_power_domain_on: get_device(113) failed (-19)
    No : 1 4 *****
    CpswPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    Cp

    U-Boot 2019.01-dirty (Nov 03 2020 - 18:44:53 +0000)

    SoC: J721E PG 1.0
    Model: Texas Instruments K3 J721E SoC
    swMcm_enablePorts() Successfully opened MAC port: 1 - 0
    CReading on-board EEPROM at 0x50 failed 1
    Board: J721EX-PM1-SOM rev E2
    DRAM: p4 GiB
    swMcm_enablePorts() Flash: 0 Bytes
    MMC: ****sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from SPI Flash... Oti_sci_power_domain_on: get_device(103) failed (-19)
    pening MAC Port No : 2 5 *****
    CpswPhy_bindDriver: PHY 2: OUI:000732 Model:00 Ver:00 <-> 'generic' : OK
    CpswMcm_enablePorts() Successfully opened MAC port: 2 - 0
    PHY 0 is alive
    PHY 2 is alive
    PHY 3 is alive
    Host MAC address: bb:bb:bb:bb:bb:bb
    [NIMU_NDK] CPSW has been started successfully
    CpswPhy_enableState: PHY 2: no supported caps found
    CpswPhy_enableState: PHY 2: no supported caps found
    CpswPhy_enableState: PHY 2: no supported caps found
    CpswPhy_enableState: PHY 2: no supported caps found
    CpswPhy_enableState: PHY 2: no supported caps found
    CpswPhy_enableState: PHY 2: no supported caps found

    With regards,

    Jeyaseelan

  • 0 in reply to Jeyaseelan Kirubaharan
    TI__Guru 50045 points

    Hi Jeyaseelan,

    We are reviewing your changes.

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Intellectual 775 points

    Hi Stanley,

    After re-flashed with new image we could see sometimes the system boots up properly and could see the eth1 interface listed with ifconfig from linux terminal .But most of the time we system get stuck up at the boot time with the following error.This happens only when  remote_switch_server runs from main0_0. Otherwise booting is proper.Can you let us know what could be the reason.

    ] <2020-11-06> <12:56:06.441> ***
    0038: [1] <2020-11-06> <12:56:06.441> CpswMcm_enablePorts() Successfully opened MAC port: 0 - 0
    0039: [1] <2020-11-06> <12:56:06.507> CpswMcm_enablePorts() ****Opening MAC Port No : 1 4 *****
    0040: [1] <2020-11-06> <12:56:06.573> CpswPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> '
    0041: [1] <2020-11-06> <12:56:06.637> U-Boot 2019.01-dirty (Nov 03 2020 - 18:44:53 +0000)
    0042: [1] <2020-11-06> <12:56:06.638> SoC: J721E PG 1.0
    0043: [1] <2020-11-06> <12:56:06.638> Model: Texas Instruments K3 J721E SoC
    0044: [1] <2020-11-06> <12:56:06.639> dp83867' : OK
    0045: [1] <2020-11-06> <12:56:06.650> CpswMcm_enablePorts() Successfully opened Reading on-board EEPROM at 0x50 failed 1
    0046: [1] <2020-11-06> <12:56:06.703> Board: J721EX-PM1-SOM rev E2
    0047: [1] <2020-11-06> <12:56:06.703> DRAM: 4 GiB
    0048: [1] <2020-11-06> <12:56:06.704> MAC port: 1 - 0
    0049: [1] <2020-11-06> <12:56:06.714> CpsFlash: 0 Bytes
    0050: [1] <2020-11-06> <12:56:06.715> MMC: wMcmsdhci@4f80000: 0, sdhci@4fb0000: 1
    0051: [1] <2020-11-06> <12:56:06.748> Loading Environment from SPI Flash... _enablePorts() ****Opening MAC Port No : 2 5 *****
    0052: [1] <2020-11-06> <12:56:06.792> CpswPhy_bindDriver: PHY 2: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    0053: [1] <2020-11-06> <12:56:06.856> CpswMcm_enablePorts() Successfully opened MAC port: 2 - 0
    0054: [1] <2020-11-06> <12:56:06.921> PHY 0 is alive
    0055: [1] <2020-11-06> <12:56:06.932> PHY 2 is alive
    0056: [1] <2020-11-06> <12:56:16.966> ti_sci_get_response: Message receive failed. ret = -110
    0057: [1] <2020-11-06> <12:56:16.968> RM_RA:Mbox config send fail -110
    0058: [1] <2020-11-06> <12:56:16.969> TISCI reset ring fail (-110) ring_idx 96
    0059: [1] <2020-11-06> <12:56:26.986> ti_sci_get_response: Message receive failed. ret = -110
    0060: [1] <2020-11-06> <12:56:26.986> RM_RA:Mbox config send fail -110
    0061: [1] <2020-11-06> <12:56:26.987> TISCI ring free fail (-110) ring_idx 2

    After the above print, further booting is not happening.  Can you let us know what could be the reason for the same. Have attached both the issue log and the working logs attached.

    With regards,

    Jeyaseelan11_06_2020.zip

     

  • 0 in reply to Jeyaseelan Kirubaharan
    Intellectual 775 points

    Adding few more information 

    In the issue case the U_boot is getting stuck, with above highlighted traces at the entry. The following traces of establishing connection to NIMU to switch software(eth_switch_main_0_0) is not happening.

    In the working case  the below traces related to NIMU is seen from the switch software.

    Host MAC address: bb:bb:bb:bb:bb:bb
    [NIMU_NDK] CPSW has been started successfully. 

    Does U_boot try to establish communication with R5F switch via ipc as the error traces reg from u_boot  look related to the the same? 

    With regards,

    Jeyaseelan

  • 0 in reply to Jeyaseelan Kirubaharan
    TI__Guru 50045 points

    Close this post here and move the discussion to private forum.

  • 0 in reply to Stanley Liu
    Intellectual 775 points

    Thanks Stanley ,, the root cause of the issue is found. Some how there is a conflict is seen between the debug UART port used in  switch firmware(wakeup domain UART) and the DMA resource allocation for eth packet  .The issue is not observed if we comment all the trace print (basically removed the function definition of cpsw_apputils_print() in psdk). Further investigation will be done from the private forum.

    With regards,

    Jeyaseelan