TDA4VM: OSPI and QSPI frequency is not setting properly

Shiva Shankar

Part Number: TDA4VM

Hi Team,

While testing the OSPI and QSPI flash devices in u-boot using driver in u-boot, I found the requested frequency is not set properly.

Below are the observations made :

Reference clock = 133333333 Hz and spi-max-frequency = <50000000>; is used through out.

1) OSPI test

PHY MODE : Enabled in the dts file

Read happens in octal mode and frequency is set to 133 MHz

Write happens in SPI mode and frequency is set to 133 MHz

Note : This behaviour is when I comment out the "cdns,phy-mode" in k3-j721e-som-p0.dtsi under

&ospi0 {

.....

cdns,phy-mode

....

}

But in actual as per the clock tree diagram, when phy mode is enabled then the controller has to route the reference clock as it is to the device input clock pin, and

when we disable the phy mode, the clock divider will come in action and gives the further divided clock to the device input clock pin. Kindly check if it is a bug because

the behaviour is vice-versa i.e., when we comment out the "cdns,phy-mode" the phy mode is enabled.

2) QSPI test

PHY MODE : Disabled in the dts file

Read happens in Quad mode and frequency is set to 33 MHz

Write happens in SPI mode and frequency is set to 33 MHz

3) QSPI test

PHY MODE : Enabled in the dts file

Read happens in Quad mode but frequency is set at 33 MHz as against expected 133 MHz

Write happens in SPI mode but frequency is set at 33 MHz as against expected 133 MHz

We are unable to figure out whether there is a bug in the upstream code itself. And unable to draw a conclusion on this.

Kindly help us on this.

Regards,

Shiva Shankar K.

over 5 years ago

0 Shiva Shankar over 5 years ago

Prodigy 240 points

Hi Team,

A gentle reminder!!!

Kindly shed some light.

Regards,

Shiva Shankar K.

0 Keerthy J over 5 years ago in reply to Shiva Shankar

TI__Guru**** 164630 points

Hi Shiva Shankar,

I need some time on this to check at my end. I will get back to you on this by Tuesday.

Best Regards,
Keerthy

0 Keerthy J over 5 years ago in reply to Keerthy J

TI__Guru**** 164630 points

Hi Shiva Shankar,

We need more details on this:

1) SDK Version used.
2) Is the issue you observe is in u-boot or Kernel?
3) Is it a custom board is TDA4 EVM from TI?

Best Regards,
Keerthy

0 Shiva Shankar over 5 years ago in reply to Keerthy J

Prodigy 240 points

Hi Keerthy,

Thank you and please find the details below :

1) ti-processor-sdk-linux-automotive-j7-evm-07_00_01 is the SDK.

2) We tested it from the u-boot

3) Yes, it is a custom board based on tda4vm processor on Jacinto 721E EVM.

Looking forward to hearing from you.

Regards,

Shiva Shankar K.

0 Keerthy J over 5 years ago in reply to Shiva Shankar

TI__Guru**** 164630 points

Hi Shiva Shankar,

One information from our SPI expert:
PHY calibration and PHY mode support for QSPI is not supported.

Let us focus on OSPI as QSPI is not enabled on our release by default & i believe this
property definition holds good for OSPI. I dumped the Reference clock for OSPI in kernel:

k3conf dump clock | grep DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK
| 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666

So OSPI_RCLK is 166 MHz in Linux kernel. Can you try the same command on your kernel?

Also what is the OSPI Flash part on your custom board? Is it same as the one on TDA4?

Can you also share(Attach a patch0 the changes that you have done for getting the OSPi to work on your custom board?
Finally how are you concluding that frequency is 33MHz? Are you using an oscilloscope?

Best Regards,
Keerthy

0 Shiva Shankar over 5 years ago in reply to Keerthy J

Prodigy 240 points

Dear Keerthy,

1) We would like to know the reason why phy mode for QSPI is not supported? Because as per our understanding the lower level driver is 'cadence_qspi.c' ( in uboot under path : ./drivers/spi ) for both OSPI and QSPI. In kernel, it is 'cadence-quadspi.c' ( under the path : ./drivers/mtd/spi-nor).

2) Please find the coloured text for our dump in the kernel.

root@j7-evm:~# k3conf dump clock | grep DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK
| 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 |
| 103 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 |
| 103 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 |

3)No, we are using ISSI devices and the part numbers are :

OSPI part no. : IS25WX256 and

QSPI part no. : IS25WP256

4) We have made the below changes

a) In the struct for ISSI device :

static const struct flash_info spi_nor_ids[] = {

.....

{
"is25wx256", INFO(0x9d5b19, 0, 128 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_OPI_DTR |
SPI_NOR_4B_OPCODES)
},

.....

}

b) We added the below code snippet to support ospi and qspi. for qspi we enabled quad enable bit in the status register.

static void issi_set_default_init(struct spi_nor *nor)
{
switch(JEDEC_DEV(nor->info))
{
/* IS25WXxxx OSPI device*/
case 0x5B:
nor->params.change_mode = spi_nor_micron_set_octal_ddr_mode;
nor->params.adjust_op = spi_nor_micron_adjust_op;
break;
/* IS25WPxxx QSPI device*/
case 0x70:
nor->params.quad_enable = macronix_quad_enable;
nor->params.set_4byte = issi_set_4byte;
break;
default:
break;
}
}

c) We are calling this 'issi_set_default_init()' inside the 'spi_nor_manufacturer_init_params()' as below :

static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
{

.....
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {

case SNOR_MFR_ISSI:
issi_set_default_init(nor);

......

}

5) Yes, we used oscilloscope to measure the frequencies.

Regards,

Shiva Shankar K.

0 Keerthy J over 5 years ago in reply to Shiva Shankar

TI__Guru**** 164630 points

Hi Shiva Shankar,

I checked with our SPI expert and it seems that OSPI support is present but QSPI is not
added. As the TDA4 has a better flash part in OSPI with higher performance.

On the clock frequency as you see from your dump:
| 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 |

is 166 MHz. I am not sure why the frequency is seen as 133MHz.

We request you to provide the following as the flash parts are different:

Datasheet (Is it exactly same as Micron Mt35x then we don't need it)
All changes make to all dts files (prefer full patch or zip of all files)
all changes to spi-nor.c file (and any changes to cadence-quadspi.c as well)
full bootlog currently (to see what works and what does not)

Since phy-mode is being the topic of importance:

register dump of 0x47040000 - 0x47040100 with and without cdns,phy-mode property
So we can check the difference in the configuration.

Best Regards,
Keerthy

0 Shiva Shankar over 5 years ago in reply to Keerthy J

Prodigy 240 points

Keerthy,

Please find the link shared to download the attachment comprising those requested documents.

https://drive.google.com/file/d/1az6YgCR7k0-Rf-zP2y_OKOMlqjq2TfOI/view?usp=sharing

The OSPI CLK frequency of 133 MHz is fine with us rather the 166MHz because of the ISSI silicon limitations at the moment, the

device is limited to function at 133 MHz.

My question is mainly due to the in-effect 'phymode' entry in the dts file and you can find the results for various combinations

experimented both on our custom board as well as on the EVM (J721E) board, find the experiment results in the xls sheet in the attachment.

We request you to work out our issue for QSPI device(data sheet attached).

Regards,

Shiva Shankar K.

0 Keerthy J over 5 years ago in reply to Shiva Shankar

TI__Guru**** 164630 points

Hi Shiva Shankar,

I am not able to open that link in our network. If that is not too big can you attach the zip here itself?

Also:

shiva shankar35669 said:

We request you to work out our issue for QSPI device(data sheet attached).

Issue as in support with phymode? That is not present in the upstream as well at the moment.
Can you elaborate your request on QSPI?

Best Regards,
Keerthy

0 Shiva Shankar over 5 years ago in reply to Keerthy J

Prodigy 240 points

Hi Keerthy,

Here attaching the zip file comprising all the documents.

/cfs-file/__key/communityserver-discussions-components-files/791/to_5F00_ti.zip

We did not seek QSPI with phy mode enabled( we understood when you elaborated it in the very first reply), we only sought your help to set the frequency up anything above 33.33 MHz for QSPI, also you can see the frequency was always setting up at 33.33 MHz. Kindly refer the .xls sheet attached.

Regards,

Shiva Shankar K.

0 Keerthy J over 4 years ago in reply to Shiva Shankar

TI__Guru**** 164630 points

Hi Shiva Shankar,

Thanks a lot for all the details. This will be really helpful in checking with our SPI experts. I will
respond back as soon as i have responses from them on QSPI question which i think is our topic
of interest.

Best Regards,
Keerthy

0 Keerthy J over 4 years ago in reply to Keerthy J

TI__Guru**** 164630 points

Hi Shiva Shankar,

Our QSPI expert reviewed the clock frequencies & the response is that PHY mode is not used with QSPI
& this is the expected Gap. QSPI is not currently supported with SDK 7.0 as of now. As you know they
were enabled with patches on top. So only boot is verified with that PHY mode support is not validated with
that so we have that limitation on QSPI. So we cannot really increase the frequency of QSPI with the current
set of patches.

Hope you can resolve the issue.

Best Regards,
Keerthy

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TDA4VM: OSPI and QSPI frequency is not setting properly