AM3358: AM3358 I2C Bus Clear Operation

Peng Liu50174

Part Number: AM3358

Hi,

In the AM3358 Technical Reference Manual section 21.3.8, the note says when SCL is stuck low, the Bus Clear operation is supported.

As there is no status bit in the I2C status register indicating SCL or SDA stuck low state, then how to evoke this Bus Clear operation?

Also the I2C status register does not have bit for I2C transaction timeout event, then how to monitor the timeout?

Thanks,

Peng,

over 4 years ago

0 Max Kross1 over 4 years ago

TI__Intellectual 2180 points

Hello,

Are you using RTOS or Embedded Linux?

Thanks,

Max

0 Peng Liu50174 over 4 years ago in reply to Max Kross1

Expert 1500 points

Hi, Max,

We are using Linux. The TI SDK is 6.0.

Thanks,

Peng

0 Max Kross1 over 4 years ago in reply to Peng Liu50174

TI__Intellectual 2180 points

Hi Peng,

I've assigned an I2c embedded linux expert to this thread, you should expect to hear from him soon.

Thanks,

Max

0 Nick Saulnier over 4 years ago in reply to Max Kross1

TI__Guru** 101010 points

Hello Peng,

The Linux driver i2c-omap.c should take care of implementing the Bus Clear operation. If omap_i2c_wait_for_bb() times out, it calls omap_i2c_recover_bus to try to recover the bus.

Regards,

Nick

0 Peng Liu50174 over 4 years ago in reply to Nick Saulnier

Expert 1500 points

Hi， Nick,

This omap_i2c_wait_for_bb() can not handle the busy state in the middle of the one read transaction.

We observed that :CPU AM3358 issue slave (battery charger) address with write bit set, and set the register address to read back. I2C slave positively acknowledges CPU but then pulls SCL to low more than 40ms (more than 35ms maximum SMbus timeout ), then the ICL signal is released. CPU continues the previous read--issuing slave address with read bit set, instead of restart the transaction---- issuing slave address with write bit set, sending address to read, issuing slave address with read bit set, reading the content.

So is there any patch or code handle such SMbus timeout in the middle of one transaction?

Thanks,

Processors

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AM3358: AM3358 I2C Bus Clear Operation