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TDA4VM: How to realize PCIe communication between two TDA4

buaawkp
Expert 1345 points
Part Number: TDA4VM

Hi，

We want to test the PCIe communication between two TDA4 chips, marked TDA4_A, TDA4_B, and transfer image data between the two TDA4 chips through the PCIe interface.

The PCIe clock TDA4_A on our hardware provides the clock to TDA4_B. The circuit schematic diagram is as follows:


At the same time, we can also choose to provide clocks to the PCIe interfaces of TDA4_A and TDA4_B through an external clock by use R3004 and R3006.

When using an external clock, we follow the method in section 3.2.2.8 of ti-processor-sdk-linux-automotive-j7-evm-07_00_00 userguide. TDA4_A uses rc mode, TDA4_B uses ep mode, and TDA4_A can correctly read the nodes of TDA4_B .

But when we use TDA4_A to provide a clock to TDA4_B, TDA4_A uses rc mode, TDA4_B uses ep mode, and TDA4_A cannot read the nodes of TDA4_B.

Questions are as follows

1. Use TDA4_A to provide clock to TDA4_B, what do we need to modify to realize the function of TDA4_A and TDA4_B PCIe communication？

2. In the userguide Multi-chip Video-Capture Application using PCIe Backplane example of vision_app of psdk_rtos_auto_j7_06_02_00_21, I can realize image transmission between two TDA4s. But the two TDA4s are in RC mode, and a TDA4 is needed as a backplane.

If my TDA4_A is configured as RC and TDA4_B is configured as EP, are there any relevant examples to realize the image transmission of both? If not, how can we modify the Multi-chip Video-Capture Application example to achieve this function?

Best Regards！

Kepei

  • 0
    Expert 1345 points

    Is there an expert who can answer my question?

  • 0 in reply to buaawkp
    TI__Mastermind 23125 points

    Buaawkp, 

    Current SDK does not support outputting refclk. We have internal work to enable and test it, but not completed yet. 

    On the demo user guide of  Multi-chip Video-Capture Application using PCIe Backplane example, can you send me the direct link? 

    To use one of the SOC as backplane, you may reference:

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_Backplane.html

    This guide is in reference to Linux driver, but the concept of of how to configure BARS in the Backplan device applies to RTOS example too. 

    If you have additional questions about the Visionapp modules, I can let one of my colleague to answer, once you send me the direct link.

    regards

    Jian

  • 0 in reply to jian35385
    Expert 1345 points

    Hi Jian，

    Thanks for your reply!

    This is the link of "Multi-chip Video-Capture Application using PCIe Backplane example" in PSDK06_02_00_21:

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/06_02_00_21/exports/docs/vision_apps/docs/user_guide/APP_PCIE_VIDEO.html

    In psdk_ rtos_ auto_J7_07_00_00_11, this example was deleted.

    In this example, the ntb_peer module needs to be used first, but this module is deleted in the ti-processor-sdk-linux-automotive-j7-evm-07_00_00 kernel.

    So my question is:
    1. One piece of TDA4_A is used as RC and the other TDA4_B is used as EP. Is it possible to use pcie_tx_node and pcie_rx_node in vision_apps/kernels/sample/r5f/ to realize video transmission?

    2. What changes do I need to make in the linux kernel and driver?

    Thanks!

    Kepei

  • 0 in reply to buaawkp
    TI__Mastermind 23125 points

    Kepei, 

    You can use RC-EP configuration to perform display-capture functions on each side. But I don't think you you can use the nodes as-is. I will ask my colleague to check the content of the scripts:

    Capture EVM:

    ./run_app_pcie_video_source.sh

    Display EVM:

    ./run_app_pcie_video_sink.sh

    and comment. 
    Jian
  • 0 in reply to jian35385
    Expert 1345 points

    Hi Jian，

    Thanks！

    I tested it according to your suggestion and used it to receive and display the image on the EP side, but the following error occurred in EP side:
    It looks like the address translatedAddress is incorrect：

    [MCU2_0]    100.280481 s: TranslationCfg.sizeInBytes is 0x10000, baseAddress is 0xadff0000, translatedAddress is 0xffffffffffffffff
    [MCU2_0]    100.280572 s: appPcieSetupRat(): Error in CSL_ratConfigRegionTranslation()

    In the ntb_peer driver, the translatedAddress address is configured during net_peer modprobe.

    Best Regards.

    Kepei

  • 0 in reply to buaawkp
    TI__Intellectual 1385 points

    Hi Kepei,

    In order to achieve similar functionality between RC and EP as that of NTB, a new "endpoint function" and a new "host side driver" should be written both providing functionality similar to ntb peer.

    Endpoint Function Driver:

    You can refer drivers/pci/endpoint/functions/pci-epf-test.c and write a  driver to provide similar functionality as that of ntb_peer for the endpoint side.

    Here you have to use pci_epc_map_addr() for mapping remote address and pci_epc_set_bar() for letting RC access EP memory.

    Host Side Driver:

    You can refer drivers/misc/pci-endpoint-test.c and write a driver to provide similar functionality as that of ntb_peer for the host side.

    struct pci_dev *pdev (resource member) will have the physical address to access EP memory. You can refer how local address is passed to remote device in pci_endpoint_test_copy(), pci_endpoint_test_read(), pci_endpoint_test_write()

    Thanks

    Kishon

  • 0 in reply to KISHON VIJAY ABRAHAM
    Expert 1345 points

    Hi Kishon

    Thank you so much for your suggestion!

    We have implemented the functions of rc and ep. At present, our problem is how to generate the internal clock

    Compiler/TDA4VM: Are there write protection restrictions on the operation of the CTRLMMR_PCIE_REFCLK1_CLKSEL...

    e2e.ti.com
    Part Number: TDA4VM Tool/software: TI C/C++ Compiler Hello, ti experts， My SDK version is PSDK-07_01_00_11. Are there write protection restrictions on the

    Thanks

    Kepei

  • 0 in reply to buaawkp
    TI__Guru** 113810 points

    Hi Kepei,

    Thanks for the confirmation, we are actively working on the other thread related to internal clock, we should have an update in the next few days.

    Lets continue discussion there.

    Closing this thread for now.

    Regards

    Karthik