In the TISCI X509 certificate system firmware debug extension, The structure of the field is shown below in ASN.1 notation.
UID-Debug ::= SEQUENCE｛
uid OCTET STRING, -- unique ID of the device for which this certificate applie
debugCtrl INTEGER, -- debug control information
coreDbgEn INTEGER, -- Core IDs for which debug must be enabled
coreDbgSecEn INTEGER, -- Core IDs for which secure debug must be enabled
}
The debug control data is decoded as a structure below:
struct sdbg_debug_ctrl {
u16 debug_priv_level;
u16 hw_key_hide_flags;
u8 debug_core_sel[MAX_CPU_CORES]；
u8 sec_debug_core_sel[MAX_CPU_CORES];
}
Whether debugCtrl, coreDbgEn, coreDbgEn form struct sdbg_debug_ctrl，In other words,
debugCtrl={u16 debug_priv_level; u16 hw_key_hide_flags};
coreDbgEn=debug_core_sel[MAX_CPU_CORES]；
coreDbgSecEn=sec_debug_core_sel[MAX_CPU_CORES]；
Is that right？
If so, then MAX_CPU_CORES=4; Why is the maximum number of CPU cores only 4？
In addition, is the certificate format used by TISCI_MSG_OPEN_DEBUG_FWLS der or pem?
