Hi TI,
I have two TDA4VM connected via PCIe, one is RC the other is EP. The output of lspci -v for one physical function says the following:
0001:01:00.0 Unassigned class [ff00]: Texas Instruments Device b00d
Flags: bus master, fast devsel, latency 0, IRQ 42
Memory at 1c7da400 (32-bit, non-prefetchable) [size=256]
Memory at 1c7d9800 (32-bit, non-prefetchable) [size=512]
Memory at 1c7d8000 (32-bit, non-prefetchable) [size=1K]
Memory at 1c7c0000 (32-bit, non-prefetchable) [size=16K]
Memory at 1c700000 (32-bit, non-prefetchable) [size=128K]
Memory at 18100000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [80] Power Management version 3
Capabilities: [90] MSI: Enable- Count=1/2 Maskable- 64bit+
Capabilities: [b0] MSI-X: Enable- Count=2 Masked-
Capabilities: [c0] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Alternative Routing-ID Interpretation (ARI)
Capabilities: [150] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [160] Power Budgeting <?>
Capabilities: [1b8] Latency Tolerance Reporting
Capabilities: [1c0] Dynamic Power Allocation <?>
Capabilities: [200] Single Root I/O Virtualization (SR-IOV)
Capabilities: [300] Secondary PCI Express
Capabilities: [400] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [440] Process Address Space ID (PASID)
Capabilities: [4c0] Virtual Channel
Capabilities: [5c0] Address Translation Service (ATS)
Capabilities: [640] Page Request Interface (PRI)
Capabilities: [900] L1 PM Substates
Capabilities: [a20] Precision Time Measurement
Kernel driver in use: pci-endpoint-test
Kernel modules: pci_endpoint_test, ntb_hw_epf
So in my understanding, that means, that by default, all 6 BARs are configured with memory space going from 256 Bytes op to 1 MByte. Reading in The TRM at chapter 12.2.3.5.1.5 gave me an hint on how to set the register so I get a 32 Bit non prefetchable BAR. But I still do not know which file is responsible for this setting. I found one promising hint in the DTS file k3-j721e-main.dtsi:
pcie0_rc: pcie@2900000 {
compatible = "ti,j721e-pcie-host";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
cdns,max-outbound-regions = <16>;
cdns,no-bar-match-nbits = <64>;
vendor-id = /bits/ 16 <0x104c>;
device-id = /bits/ 16 <0xb00d>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
<0 0 0 2 &pcie0_intc 0>, /* INT B */
<0 0 0 3 &pcie0_intc 0>, /* INT C */
<0 0 0 4 &pcie0_intc 0>; /* INT D */
pcie0_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
};
};
But I am not sure on how to decode this to get the information provided by the TRM about the BARs. So where exactly in the source code are BARs configured? And could you please give a feedback, that my previos assumptions about the BARs are correct?
Thanks.
