TMS320C6657: Same Write Access time/cycles even though Cache Enabled or Disabled

Hi,

I’ve received a question from my customer regarding memory access cycles on C665x.

When they measured time of read/write access from/to L2 SRAM and L3 MSM SRAM, they got the following results.

Case of Disabled L1D cache

L3 Read             31.3       26.605

L2 Read             19.6       16.66

L3 Write              7            5.95

L2 Write              7            5.95

Case of Enabled L1D cache

L3 Read             7.4         6.29

L2 Read             7.4         6.26

L3 Write              7            5.95

L2 Write              7            5.95

* Core frequency is 850MHz in the both cases.

Why Write Access time/cycles are the same in spite of cache was enabled/disabled ?

Is there any buffer between core and SRAM ?

Not sure, but L2 weight should be 6 cycles, 19.6 cycles of L2 Read with no cache looks longer.

Could you tell them why L2 read took 19.6 cycles if you know something ?

Regards,

Hideaki