OMAPL138 memory protection questions

Hello:

I got the following questions from a customer. Can I get some guidance?

1.  L1PMPPA xx ,L1PMPLK0,L1PMPLK1,L1PMPLK2,L1PMPLK3,L1PMPLKCMD ,L1DMPPAxx ,L1DMPLK0, L1DMPLK1,L1DMPLK2,L1DMPLK3,L1DMPLKCMD,L2MPPAxx,L2MPLK0,L2MPLK1,L2MPLK2,L2MPLK3,L2MPLKCMD   default value  is what?

2. The MPU generates two interrupts:an address errorinterrupt(MPU_ADDR_ERR_INT)and a protection interrupt(MPU_PROT_ERR_INT). Theinterruptsfrom both MPUs are combined withthe bootconfiguration moduleinto a singleinterrupt called MPU_BOOTCFG_ERR.The combined interrupt is routed to the ARM and DSP interrupt controllers.  

          how is The MPU interrupt Response???  How is  The MPU interrupt Related to Interrupt vector??

 /**========================================================**/
/** 函数名称：DSP_L1PMP_REG_Init
@brief：DSP的L1P memory protect 配置寄存器初始化
@return  ：无
**========================================================**/
void  DSP_L1PMP_REG_Init(void)
{
// WORD wLoop;
 for(wLoop = 0;wLoop < 32;wLoop++)
 {
  L1PMP_REG->MPPA[wLoop] = 0x0;//
 }
 //L1PMP_REG->MPFAR;  //READ ONLY
 //L1PMP_REG->MPFSR;  //READ ONLY        
 //L1PMP_REG->MPLKSTAT  //READ ONLY
     
 L1PMP_REG->MPLKCMD  = 0X00;  //Unlock the lock provided that the software executed the sequence correctly
 L1PMP_REG->MPFCLR   = 0X01;  //clar   MPFAR and MPFSR
 L1PMP_REG->MPLK0    = 0;     
 L1PMP_REG->MPLK1    = 0;     
 L1PMP_REG->MPLK2    = 0;     
 L1PMP_REG->MPLK3    = 0;

 /**========================================================**/
/** 函数名称：DSP_L1DMP_REG_Init
@brief：DSP的L1D的memory protect 配置寄存器初始化
@return  ：无
**========================================================**/
void  DSP_L1DMP_REG_Init(void)
{
 WORD wLoop;
  
 for(wLoop = 0;wLoop < 32;wLoop++)
 {
  L1DMP_REG->MPPA[wLoop] = 0x00FFF6;//
 }
 //L1PMP_REG->MPFAR;  //READ ONLY
 //L1DMP_REG->MPFSR;  //READ ONLY 
 //L1PMP_REG->MPLKSTAT; //READ ONLY     
    
 L1DMP_REG->MPLKCMD  = 0X0;//Unlock the lock provided that the software executed the sequence correctly
 L1DMP_REG->MPFCLR   = 0X01; //clar   MPFAR and MPFSR
 L1DMP_REG->MPLK0    = 0;     
 L1DMP_REG->MPLK1    = 0;     
 L1DMP_REG->MPLK2    = 0;     
 L1DMP_REG->MPLK3    = 0;        

}

Thanks,

Pradhyum