Other Parts Discussed in Thread: TLV320ADC3101, SYSBIOS, PCM1864
We have a hardware design connecting a microphone array to the C674x and we have intermittent issues maintaining phase alignment of the microphone data. The microphones connect to the DSP through multiple stereo ADCs(TLV320ADC3101) in the TDM fashion and intermittently the audio from one or more ADCs is one sample delayed when compared to the other(s).
During our DSP boot process the McASP and the connected hardware is configured through a fixed startup sequence that has been derived from TI references - e.g. the McASP startup examples in pspdrivers and the guidelines provided in app notes such as SLAA508A. After repeated boot up tests the phase alignment can be evaluated and a particular DSP build/image falls into one of three cases - 1) it always starts up with correct phase alignment, 2) it never starts up with correct phase alignment or 3) Sometimes it is phase aligned and after some reboots it is not. Currently, whenever we have a DSP build that falls into case 2 or 3 we tweak a task delay value in the McASP & ADC startup sequence to get the phase alignment back to case 1 which is somewhat arbitrary and not a very methodical process. So the question is simply this, how can we methodically configure the McASP and ADCs at bootup to guaranteed phase alignment of the microphone data?
Some relevant notes & observations are listed here:
a) We are using CCS4.2 tool chain with DSP BIOS 5.41.10.36.
b) All ADC sampling is governed by a single frame pulse (@16KHz rate) from the McASP so the instantaneous sampled data in the ADCs should be correct.
c) We invoke the McASP serializers to collect the sampled data every TDM frame into 2ms buffers for DSP processing.
d) Our DSP image is large enough that we must place significant portions of code into external DDR memory including some of DSP BIOS and the PSP/EDMA drivers.
e) We have experienced cases of broken phase alignment after only a simple rearrangement of the DDR memory map when code changes were made unrelated to the McASP/ADC startup procedure. In these cases it is assumed that either DDR page boundaries or cache line fill procedures are affecting the timing enough in the startup sequence of the McASP and ADC hardware to cause the problem.
Bottom line we would like to boot up the DSP without any such sensitivity to timing in the DSP subsystem and guarantee phase alignment of our microphone/ADC data. Perhaps there is a flush/resync sequence, we're not aware of, to ensure we align the McASP/serializers properly?
