Part Number: TDA2SX
Hi,
in my test(used tda2xx_evm_bios_all on windows os, and chose tidlOD usecase), I often need a lot of transfers by System_linkControl(),
it waii cause system assert, the assert message link this:
[IPU1-0] 211.556945 s: Assertion @ Line: 524 in utils_mbx.c: ackQue != NULL : failed !!! [IPU1-0] 211.557311 s: Assertion @ Line: 524 in utils_mbx.c: ackQue != NULL : failed !!!
So I judge I need to increase mailbox ack queue numbers,
then i find the #define in C:\PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\links_fw\src\rtos\utils_common\include\utils_mbx.h in line:139 like this:
/** ******************************************************************************* * \brief Maximum number of ack queues.This allows multiple tasks to wait * on different ack msgs ******************************************************************************* */ #define UTILS_MBX_ACK_QUE_CNT_MAX (4U)
Is it defined the mailbox ack queue numbers is 4? If true, can I increase it? because I tried to increase it to 8,
but it will cause crash on system boot and and provide no feedback like this:
SDK3_05_TDA2xx_SBL_V1.0 SBL_OPP_HIGH SBL Initial Config Failed DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed TI EVM PAD Config Completed ERROR: HW-Leveling time-out DDR Config Completed App Image Download Begins SD Boot - file open completed successfully MPU CPU0 Image Load Completed IPU1 CPU0 Image Load Completed IPU1 CPU1 Image Load Completed DSP1 Image Load Completed DSP2 Image Load Completed EVE1 Image Load Completed EVE2 Image Load Completed EVE3 Image Load Completed EVE4 Image Load Completed App Image Download Completed Putting MPU CPU1 in Off mode EVE MMU configuration completed EVE MMU configuration completed EVE MMU configuration completed EVE MMU configuration completed ***************************************************************** PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles SBL Initial Config Cycles - 85438 (7.29 ms) SOC Init Cycles - 264250 (22.54 ms) DDR Config Clock Cycles - 181517 (15.48 ms) App Image Load Cycles - 146772656 (12524.59 ms) Slave Core Bootup Cycles - 323025 (27.56 ms) SBL Boot-up Cycles - 147628220 (12597.60 ms) Time at which SBL started IPU1_0 - 273481 (23.33 ms) ***************************************************************** Jumping to MPU CPU0 App
I can't know where the error occurred,
please help me to resolve the problem, thanks you.
