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TDA4VM: Configuration of MCU PLLs

Andrzej Bodura
Prodigy 80 points
Part Number: TDA4VM

Hi,

When is exactly the configuration of the MCU PLL executed? According to the Boot Process Flow from chapter 4.2.3 of the Technical Reference Manual, right after the Image Integrity check, the configuration of MAIN Domain PLLs is performed. However, there is no step dedicated to the configuration of MCU Domain PLLs.

 

Best Regards,

Andrzej

  • 0
    TI__Mastermind 30245 points

    Hi Andrej

    The MCU PLL gets locked by the DMSC ROM during boot. Please refer to the TRM diagram : Figure 4-3. Boot Process

    Thanks and Regards

    Piyali

  • 0 in reply to Piyali Goswami
    Prodigy 80 points

    Hello Piyali,


    Thanks for the response, but you completely misunderstood my question. I am talking about the set of PLL configuration parameters that are described in chapter 4.3.14 of the TRD document and selected by MCU_BOOTMODE[02:00] pins. I asked you why in the Boot Process Flow, there is no step dedicated to configuring MCU_PLLs in accordance with PLLs configuration selected with MCU_BOOTMODE pins. I do not talk about the configuration of MCU PLLs to the needs of the booting process. I am interested in the configuration of MCU_PLLs to the needs of a normal run time.

     

    I hope that the question is clear now.

     

    Best Regards,

    Andrzej

  • 0 in reply to Andrzej Bodura
    TI__Mastermind 30245 points

    Andrej

    There are a couple of things here:

    During the boot based on the BOOTMODE pins, ROM will program the MCU_PLL according to Table 4-45. PLL Configuration for MCU_PLL0, MCU_PLL2, Main PLL0, and PLL3

    In the SYSFW initialization again the MCU PLL is locked to a frequency corresponding to the BOOTMODE pins which are latched to the CTRLMMR_WKUP_DEVSTAT Register. The details on what is locked at the boot time which remains at run time till a frequency change request comes are as given in http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/pll_data.html

    When a frequency change is requested the final PLL lock values are calculate based on the input HFOSC clock frequency read from CTRLMMR_WKUP_DEVSTAT Register.

    Hope this helps clarify and hope I have interpreted your question correctly.

    Regards

    Piyali

  • 0 in reply to Piyali Goswami
    Prodigy 80 points

    Hi,

    So, the configuration of MCU_PLLs based on BOOTMODE pins is done in the same moment as configuration of MAIN_PLLs, correct?

    In my version of the TRM that was revised in November 2019 (link) that table which you mentioned has number 4-43 (pasted below), not 4-45. Do you have newer version of the TRM?

  • 0 in reply to Andrzej Bodura
    TI__Mastermind 30245 points

    Hi Andrej

    "So, the configuration of MCU_PLLs based on BOOTMODE pins is done in the same moment as configuration of MAIN_PLLs, correct?"

    No. The MCU PLL configuration happens from the DMSC.

    The TRM I was referring to was an old TRM (pre-release) I had locally in my hard drive. You have actually found the right table in the TRM.

    Regards

    Piyali