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CCS/66AK2G12: DSPICFGCacheEnable unresolved in PDK_K2G

James Hall2
Intellectual 260 points
Part Number: 66AK2G12
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Tool/software: Code Composer Studio

Hi I am trying to get my environment up together for a new target processor (66AK), and am hitting issues.

The current one is CSL in the PDK (pdk_k2g_1_0_16).

I am trying to enable cache using the function I eventually found by trawling various sources:

DSPICFGCacheEnable(SOC_DSP_ICFG_BASE, DSPICFG_MEM_L1D, DSPICFG_CACHE_SIZE_L1_MAX);
DSPICFGCacheEnable(SOC_DSP_ICFG_BASE, DSPICFG_MEM_L1P, DSPICFG_CACHE_SIZE_L1_MAX);

However this function is not found by the linker in the CSL archives being linked against:

ti.csl.ae66

ti.csl.intc.ae66

Also when debugging in CCS (10.1.1.00004) on the DSP core of the 66AK2G12, I cannot see registers that control the caches in the registers window.

On the previous target (OMAP-L138) I could see L2CFG register in there for example. Where can I find the equivalent for the 66AK ?

Thanks,

James

  • 0
    TI__Guru** 116170 points

    James,

    I looked at the CSL code base and looks like the C66x functions defined in the dsp_icfg.c file seem to have been included only for AM57x and TDA3/DRA7x platforms. Please check the source file being included as part of the C66x CSL build in the make file herE:

    pdk_k2g_1_0_1x\packages\ti\csl\arch\c66x\src_files_c66x.mk

    If you want to use that on K2G, you can include the dsp_icfg.c file in source and use the function.

    As far as the register view is concerned, the register view in CCS is populate using XML files that are obtained from chip design/TRM. If you have the address of this register from C674x on OMAPL138, it will be the same for C66x on K2G as well.

    Regards,

    Rahul