AM3358: DDR Length Matching and Layers

Mert,

This is documented in the data sheet in Section 7.7.2.3 "DDR3 and DDR3L Routing Guidelines".

Mert Samast1 said:

Firstly, On which layer can I draw the DDR RAM buses? Is there any difference between PCB layers? Can I draw at top layer? or which layer can I prefer for DDR RAM drawings?

On an inner layer.  You won't be able to escape all of the pins to do it on top. You'll also have better EMI on an inner layer.

Mert Samast1 said:

Secondly is about lengths. I know that, DDR RAM busses lengths have to equal each other. Should all DDR RAM busses lengths be equal to each other? Should the busses lengths within the DDR RAM groups be equal to each other?

Take a look at Table 7-67 "Signal Net Class Definitions".  Each row of that table contains a clock and its associated signals. The timings generally all relate to a single class, e.g. DQS0 and DDR_D[7:0] and DQM0 all need to maintain a specific relationship to one another, but to a degree they are independent from the other data lane and the address/control signals.

Best regards,
Brad