AM3354: EDMA Transfer Completion Interrupt

Hi, 

I am trying to transfer data via EDMA from internal memory to an FPGA through the GPMC interface. I have been able to transfer the data, however, the transfer complete interrupt is not getting triggered after the transfer finishes.

I can verify that the data is properly transferred and I have seen error interrupts occur, so this problem only has to to with the transfer complete interrupt. I am using shadow region 0 and I can verify that the interrupt enable register is getting set prior to the transfer and I am using the event set register to trigger the transfer. I have also tried using the global region registers and I see the same result.

Currently I am using channel #12, however, I have used various other channels and I have seen similar results. This transfer is a very simple transfer of 128 bytes using A-synchronized mode with A count set to 128 and B count set to 1 and C count set to 1.

After a set amount of time after initializing the transfer, no interrupts occurred and the interrupt pending register reads 0, however, the data has been properly transferred. From the documentation I understand that the IPR should have the bit set according to the TCC code set in the param options register. 

From the documentation I understand that as long as the TCINTEN bit is enabled in the param options register, the EDMA_COMPINT (irq 12) should get triggered after the transfer is complete.

Is there something missing in the documentation? 

here is the link to the related post: https://e2e.ti.com/support/processors/f/791/t/417558?AM335x-EDMA-Interrupt-documentation-Transfer-Conpletion-Interrupt-Shadow-Region-

Best,

Caroline