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TDA4VM:Questions about ethfw Phy in main R5f

Hello


I am upgrading a custom tda4 board with rtl9xxx series PHY on the main r5f, so I plan to use the tda4-evm board to study your code with psdk_rtos_auto_j7_07_00.


After startup, com2 prints as follows:

Enabling clocks for CPSW_9G!

CPSW_9G Test on MAIN NAVSS


Remote device (core : mcu2_1) .....

Host MAC address: 70:ff:76:1d:87:64

[NIMU_NDK] CPSW has been started successfully

Function:app_ethrdev_srv_cb_attach_ext_handler,HostId:0,CpswType:1

Function:app_ethrdev_srv_cb_register_mac_handler,HostId:0,Handle:a2b371c0,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:870

Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:10, Policer Entry:0Function:app_ethrdev_srv_cb_register_ip8

Failed to add Static ARP Entry

 

================LLI Table entries===========

 

Number of Static ARP Entries: 0

 

SNo.      IP Address         MAC Address 

------    -------------      ---------------

Found that IP was not set up successfully, which is inconsistent with the sample tutorial

After consulting the relevant personnel, we know that the vsc8514 board has not been successfully used in your EVM panel, but the daughter card of gei has been successfully used.

Because the EVM board we purchased does not have a Gesi sub card, I can't track the code conversion to my custom board.

Therefore, I changed the code of dp83867. C and changed its oui, model and Rev.

The output of MAIN R5F serial port is as follows:

Enabling clocks for CPSW_9G!
CPSW_9G Test on MAIN NAVSS
Dp83867_isPhyDevSupported: [debug]PHY 0: Dp83867_isPhyDevSupported? it is 1
CpswPhy_bindDriver: PHY 0: OUI:000732 Model:33 Ver:00 <-> 'DP83867' : OK
Dp83867_isMacModeSupported: [debug]PHY 0: mode is 3
PHY 0 is alive
PHY 1 is alive
PHY 2 is alive
Remote demo device (core : mcu2_0) .....
Host MAC address: 70:ff:76:1d:92:c2
Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:1
Host MAC address: 70:ff:76:1d:92:c2
[NIMU_NDK] CPSW has been started successfully
Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a212c53c,CoreKey:3
8acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:11, Policer Entry:0

Found that IP was not set up successfully So I ifconfig its ip

root@j7-evm:~# ifconfig eth1 192.168.1.88

After that,The output of MAIN R5F serial port is as follows:

Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a212c53c,CoreKey
:38acb7e6, MacAddress:70:ff:76:1d:92:c1 IPv4Addr:192.168.1.88
Failed to add Static ARP Entry

================LLI Table entries===========

Number of Static ARP Entries: 0

SNo.      IP Address         MAC Address
------    -------------      ---------------

I checked the IP On the A72,:

root@j7-evm:~# ifconfig eth1
eth1      Link encap:Ethernet  HWaddr 70:FF:76:1D:92:C1
          inet addr:192.168.1.88  Bcast:192.168.1.255  Mask:255.255.255.0
          inet6 addr: fe80::72ff:76ff:fe1d:92c1/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:39 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:6622 (6.4 KiB)

And r5f has been printing as follows:

Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a212c53c,CoreKey
:38acb7e6, MacAddress:70:ff:76:1d:92:c1 IPv4Addr:192.168.1.88
Failed to add Static ARP Entry

================LLI Table entries===========

Number of Static ARP Entries: 0

SNo.      IP Address         MAC Address
------    -------------      ---------------
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....
DHCP client timed out. Retrying.....

It seems that IP is still not set successfully.

I have a question:

What code do I need to focus on and change to use rtl9010 PHY?

What I know is to get his chip PHY address by checking the chip manual data sheet. Is there anything else?

notes:For some reason, we need to set PHY to 100 Mbps, not adaptive or 1Gbps.

 

  • Hi Hao,

    Apologies for the delay in responding to this.

    Are you trying to bring-up CPSW9G without the GESI card ? I am not sure if this is supported out of the box. I will check and get back to you on this. The IP address issue might also be related to this.

    From the pictures, it's hard to make out where you are interfacing the ethernet cable with the CPSW 9G. Can you tell ? Is it the QSGMII ?

    What code do I need to focus on and change to use rtl9010 PHY?

    Please take a look at the PHY integration guide, you will have to write your own PHY driver using the generic PHY driver provided in the SDK and the documentation.

    Regards

    Vineet

  • Because we designed our own boards,so we have to bring-up CPSW9G without the GESI cad.

    We connected 3 PHYs to 3, 4 and 6 of RGMII in tda4.

    Now we are using psdk-rtos v07.01.00 and we have changed the code.

    Now PHY can link up normally,:

    14.574775 s: Cpsw_handleLinkUp: Port 5: Link up: 100-Mbps Full-Duplex

    but it seems that PING command cannot be used on A72 terminal.

    And sometimes, after inputting ifconfig command in the shell of the board, Linux will be directly stuck and can only restart the board. If don't get stuck, i can only see eth0 without eth1.

    log is here:

    [MCU2_0]      4.125816 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_0]      4.125862 s: APP: Init ... !!!
    [MCU2_0]      4.125881 s: SCICLIENT: Init ... !!!
    [MCU2_0]      4.127025 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
    [MCU2_0]      4.127078 s: SCICLIENT: DMSC FW revision 0x14
    [MCU2_0]      4.127104 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      4.127128 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      4.127149 s: UDMA: Init ... !!!
    [MCU2_0]      4.137491 s: UDMA: Init ... Done !!!
    [MCU2_0]      4.137554 s: MEM: Init ... !!!
    [MCU2_0]      4.137597 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !
    [MCU2_0]      4.137657 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
    [MCU2_0]      4.137711 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !
    [MCU2_0]      4.137756 s: MEM: Init ... Done !!!
    [MCU2_0]      4.137775 s: FVID2: Init ... !!!
    [MCU2_0]      4.137873 s: FVID2: Init ... Done !!!
    [MCU2_0]      4.137907 s: VHWA: VPAC Init ... !!!
    [MCU2_0]      4.137929 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
    [MCU2_0]      4.138712 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.138746 s: VHWA: LDC Init ... !!!
    [MCU2_0]      4.153087 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]      4.153146 s: VHWA: MSC Init ... !!!
    [MCU2_0]      4.194883 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]      4.194942 s: VHWA: NF Init ... !!!
    [MCU2_0]      4.201926 s: VHWA: NF Init ... Done !!!
    [MCU2_0]      4.201983 s: VHWA: VISS Init ... !!!
    [MCU2_0]      4.247776 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]      4.247838 s: VHWA: VPAC Init ... Done !!!
    [MCU2_0]      4.247862 s: IPC: Init ... !!!
    [MCU2_0]      4.247896 s: IPC: 6 CPUs participating in IPC !!!
    [MCU2_0]      4.247931 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]     13.393936 s: IPC: HLOS is ready !!!
    [MCU2_0]     13.407066 s: IPC: Init ... Done !!!
    [MCU2_0]     13.407178 s: APP: Syncing with 5 CPUs ... !!!
    [MCU2_0]     13.991269 s: APP: Syncing with 5 CPUs ... Done !!!
    [MCU2_0]     13.991500 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]     13.993557 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]     13.993624 s: ETHFW: Init ... !!!
    [MCU2_0]     14.027895 s: CPSW_9G Test on MAIN NAVSS
    [MCU2_0]     14.045997 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'generic' : OK
    [MCU2_0]     14.046328 s: PHY 0 is alive
    [MCU2_0]     14.046416 s: PHY 1 is alive
    [MCU2_0]     14.046499 s: PHY 2 is alive
    [MCU2_0]     14.050342 s: ETHFW: Version   : 0.01.01
    [MCU2_0]     14.050385 s: ETHFW: Build Date: Dec 17, 2020
    [MCU2_0]     14.050411 s: ETHFW: Build Time: 20:56:35
    [MCU2_0]     14.050431 s: ETHFW: Commit SHA:
    [MCU2_0]     14.050455 s: ETHFW: Init ... DONE !!!
    [MCU2_0]     14.050480 s: ETHFW: Remove server Init ... !!!
    [MCU2_0]     14.051930 s: Remote demo device (core : mcu2_0) .....
    [MCU2_0]     14.051992 s: ETHFW: Remove server Init ... DONE !!!
    [MCU2_0]     14.074653 s: Host MAC address: 70:ff:76:1d:92:c2
    [MCU2_0]     14.102179 s: DSS: Init ... !!!
    [MCU2_0]     14.102244 s: DSS: Display type is eDP !!!
    [MCU2_0]     14.102273 s: DSS: SoC init ... !!!
    [MCU2_0]     14.102293 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
    [MCU2_0]     14.103598 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.103643 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
    [MCU2_0]     14.105463 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.105502 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
    [MCU2_0]     14.106933 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.106970 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
    [MCU2_0]     14.108153 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     14.108192 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
    [MCU2_0]     14.108632 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     14.108664 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
    [MCU2_0]     14.109069 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     14.109098 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
    [MCU2_0]     14.128436 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]     14.128476 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
    [MCU2_0]     14.129690 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]     14.129730 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.129755 s: DSS: Board init ... !!!
    [MCU2_0]     14.129777 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!!
    [MCU2_0]     14.148864 s:
    [MCU2_0] CPSW NIMU application, IP address I/F 1: 192.168.1.203
    [MCU2_0]     14.174171 s: DSS: ERROR: Turning on DP_PWR pin for eDP adapters failed !!!
    [MCU2_0]     14.174245 s: DSS: Board init ... Done !!!
    [MCU2_0]     14.194679 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
    [MCU2_0]     14.195528 s: DSS: Init ... Done !!!
    [MCU2_0]     14.195606 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]     14.195635 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]     14.195656 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]     14.196879 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0
    [MCU2_0]     14.197264 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF
    [MCU2_0]     14.197589 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1
    [MCU2_0]     14.197894 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1
    [MCU2_0]     14.198263 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2
    [MCU2_0]     14.198627 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1
    [MCU2_0]     14.198961 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1
    [MCU2_0]     14.199363 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2
    [MCU2_0]     14.199723 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1
    [MCU2_0]     14.200077 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2
    [MCU2_0]     14.200472 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX
    [MCU2_0]     14.200829 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3
    [MCU2_0]     14.201222 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4
    [MCU2_0]     14.201580 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5
    [MCU2_0]     14.201920 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6
    [MCU2_0]     14.202321 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7
    [MCU2_0]     14.202724 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8
    [MCU2_0]     14.202796 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [MCU2_0]     14.202829 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]     14.215867 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]     14.215931 s: CSI2RX: Init ... !!!
    [MCU2_0]     14.215956 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]     14.216475 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.216519 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
    [MCU2_0]     14.217403 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.217440 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
    [MCU2_0]     14.218302 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.218340 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
    [MCU2_0]     14.218823 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.218854 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
    [MCU2_0]     14.219403 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.222623 s: CSI2RX: Init ... Done !!!
    [MCU2_0]     14.222684 s: CSI2TX: Init ... !!!
    [MCU2_0]     14.222709 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]     14.223322 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.223371 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
    [MCU2_0]     14.224369 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.224407 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
    [MCU2_0]     14.225246 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.228338 s: CSI2TX: Init ... Done !!!
    [MCU2_0]     14.228393 s: ISS: Init ... !!!
    [MCU2_0]     14.228469 s: Found sensor IMX390-UB953_D3 at location 0
    [MCU2_0]     14.228530 s: Found sensor AR0233-UB953_MARS at location 1
    [MCU2_0]     14.228584 s: Found sensor AR0820-UB953_LI at location 2
    [MCU2_0]     14.228638 s: Found sensor UB9xxx_RAW12_TESTPATTERN at location 3
    [MCU2_0]     14.228751 s: Found sensor UB96x_UYVY_TESTPATTERN at location 4
    [MCU2_0]     14.228844 s: Found sensor GW_AR0233_UYVY at location 5
    [MCU2_0]     14.228906 s: Found sensor AR0220-UB953_MARS at location 6
    [MCU2_0]     14.228938 s: IssSensor_Init ... Done !!!
    [MCU2_0]     14.229039 s: vissRemoteServer_Init ... Done !!!
    [MCU2_0]     14.229116 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]     14.229186 s: UDMA Copy: Init ... !!!
    [MCU2_0]     14.236169 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]     14.236231 s: APP: Init ... Done !!!
    [MCU2_0]     14.236255 s: APP: Run ... !!!
    [MCU2_0]     14.236275 s: IPC: Starting echo test ...
    [MCU2_0]     14.238776 s: APP: Run ... Done !!!
    [MCU2_0]     14.240868 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU2_0]     14.241214 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU2_0]     14.241393 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_0]     14.241531 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_0]     14.574775 s: Cpsw_handleLinkUp: Port 5: Link up: 100-Mbps Full-Duplex
    [MCU2_1]      4.207051 s: CIO: Init ... Done !!!
    [MCU2_1]      4.207136 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_1]      4.207180 s: APP: Init ... !!!
    [MCU2_1]      4.207200 s: SCICLIENT: Init ... !!!
    [MCU2_1]      4.209106 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
    [MCU2_1]      4.209164 s: SCICLIENT: DMSC FW revision 0x14
    [MCU2_1]      4.209189 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_1]      4.209214 s: SCICLIENT: Init ... Done !!!
    [MCU2_1]      4.209234 s: UDMA: Init ... !!!
    [MCU2_1]      4.237920 s: UDMA: Init ... Done !!!
    [MCU2_1]      4.237973 s: MEM: Init ... !!!
    [MCU2_1]      4.238012 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes!
    [MCU2_1]      4.238066 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
    [MCU2_1]      4.238112 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 byt!
    [MCU2_1]      4.238183 s: MEM: Init ... Done !!!
    [MCU2_1]      4.238210 s: FVID2: Init ... !!!
    [MCU2_1]      4.238274 s: FVID2: Init ... Done !!!
    [MCU2_1]      4.238301 s: VHWA: DMPAC: Init ... !!!
    [MCU2_1]      4.238321 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
    [MCU2_1]      4.239364 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]      4.239398 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
    [MCU2_1]      4.240725 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]      4.240753 s: VHWA: DOF Init ... !!!
    [MCU2_1]      4.270802 s: VHWA: DOF Init ... Done !!!
    [MCU2_1]      4.270858 s: VHWA: SDE Init ... !!!
    [MCU2_1]      4.281444 s: VHWA: SDE Init ... Done !!!
    [MCU2_1]      4.281498 s: VHWA: DMPAC: Init ... Done !!!
    [MCU2_1]      4.281522 s: VHWA: Codec: Init ... !!!
    [MCU2_1]      4.281543 s: VHWA: VDEC Init ... !!!
    [MCU2_1]      4.296297 s: VHWA: VDEC Init ... Done !!!
    [MCU2_1]      4.296359 s: VHWA: VENC Init ... !!!
    [MCU2_1]      4.297169 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params
    [MCU2_1]      4.376337 s: VHWA: VENC Init ... Done !!!
    [MCU2_1]      4.376401 s: VHWA: Init ... Done !!!
    [MCU2_1]      4.376427 s: IPC: Init ... !!!
    [MCU2_1]      4.376464 s: IPC: 6 CPUs participating in IPC !!!
    [MCU2_1]      4.376504 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_1]     13.977720 s: IPC: HLOS is ready !!!
    [MCU2_1]     13.991099 s: IPC: Init ... Done !!!
    [MCU2_1]     13.991222 s: APP: Syncing with 5 CPUs ... !!!
    [MCU2_1]     13.991263 s: APP: Syncing with 5 CPUs ... Done !!!
    [MCU2_1]     13.991296 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_1]     13.993485 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_1]     13.993567 s:  VX_ZONE_INIT:Enabled
    [MCU2_1]     13.993594 s:  VX_ZONE_ERROR:Enabled
    [MCU2_1]     13.993613 s:  VX_ZONE_WARNING:Enabled
    [MCU2_1]     13.994777 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE
    [MCU2_1]     13.995056 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF
    [MCU2_1]     13.995360 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC1
    [MCU2_1]     13.995662 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC2
    [MCU2_1]     13.995962 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC1
    [MCU2_1]     13.996280 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC2
    [MCU2_1]     13.996342 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [MCU2_1]     13.996372 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_1]     13.996778 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_1]     13.996831 s: UDMA Copy: Init ... !!!
    [MCU2_1]     14.019336 s: UDMA Copy: Init ... Done !!!
    [MCU2_1]     14.019395 s: APP: Init ... Done !!!
    [MCU2_1]     14.019419 s: APP: Run ... !!!
    [MCU2_1]     14.019437 s: IPC: Starting echo test ...
    [MCU2_1]     14.021781 s: APP: Run ... Done !!!
    [MCU2_1]     14.022741 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[x] C66X_2[x] C7X_1[P]
    [MCU2_1]     14.025189 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[x] C7X_1[P]
    [MCU2_1]     14.026359 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_1]     14.240688 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [C6x_1 ]      4.364937 s: CIO: Init ... Done !!!
    [C6x_1 ]      4.364978 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_1 ]      4.364994 s: APP: Init ... !!!
    [C6x_1 ]      4.365001 s: SCICLIENT: Init ... !!!
    [C6x_1 ]      4.366420 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
    [C6x_1 ]      4.366433 s: SCICLIENT: DMSC FW revision 0x14
    [C6x_1 ]      4.366442 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_1 ]      4.366453 s: SCICLIENT: Init ... Done !!!
    [C6x_1 ]      4.366462 s: UDMA: Init ... !!!
    [C6x_1 ]      4.382141 s: UDMA: Init ... Done !!!
    [C6x_1 ]      4.382165 s: MEM: Init ... !!!
    [C6x_1 ]      4.382180 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes!
    [C6x_1 ]      4.382199 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_1 ]      4.382215 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 byte!
    [C6x_1 ]      4.382232 s: MEM: Init ... Done !!!
    [C6x_1 ]      4.382241 s: IPC: Init ... !!!
    [C6x_1 ]      4.382256 s: IPC: 6 CPUs participating in IPC !!!
    [C6x_1 ]      4.382270 s: IPC: Waiting for HLOS to be ready ... !!!
    [C6x_1 ]     11.731435 s: IPC: HLOS is ready !!!
    [C6x_1 ]     11.756737 s: IPC: Init ... Done !!!
    [C6x_1 ]     11.756777 s: APP: Syncing with 5 CPUs ... !!!
    [C6x_1 ]     13.991263 s: APP: Syncing with 5 CPUs ... Done !!!
    [C6x_1 ]     13.991279 s: REMOTE_SERVICE: Init ... !!!
    [C6x_1 ]     13.992078 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_1 ]     13.992145 s:  VX_ZONE_INIT:Enabled
    [C6x_1 ]     13.992156 s:  VX_ZONE_ERROR:Enabled
    [C6x_1 ]     13.992168 s:  VX_ZONE_WARNING:Enabled
    [C6x_1 ]     13.993438 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_1 ]     13.993459 s: APP: OpenVX Target kernel init ... !!!
    [C6x_1 ]     13.993860 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_1 ]     13.993881 s: UDMA Copy: Init ... !!!
    [C6x_1 ]     14.014626 s: UDMA Copy: Init ... Done !!!
    [C6x_1 ]     14.014648 s: APP: Init ... Done !!!
    [C6x_1 ]     14.023139 s: APP: Run ... !!!
    [C6x_1 ]     14.023156 s: IPC: Starting echo test ...
    [C6x_1 ]     14.024430 s: APP: Run ... Done !!!
    [C6x_1 ]     14.024854 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[.] C66X_1[s] C66X_2[x] C7X_1[P]
    [C6x_1 ]     14.025123 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[x] C7X_1[P]
    [C6x_1 ]     14.026161 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_1 ]     14.240489 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_2 ]      4.416715 s: CIO: Init ... Done !!!
    [C6x_2 ]      4.416756 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_2 ]      4.416771 s: APP: Init ... !!!
    [C6x_2 ]      4.416779 s: SCICLIENT: Init ... !!!
    [C6x_2 ]      4.418326 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
    [C6x_2 ]      4.418339 s: SCICLIENT: DMSC FW revision 0x14
    [C6x_2 ]      4.418350 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_2 ]      4.418360 s: SCICLIENT: Init ... Done !!!
    [C6x_2 ]      4.418370 s: UDMA: Init ... !!!
    [C6x_2 ]      4.436563 s: UDMA: Init ... Done !!!
    [C6x_2 ]      4.436587 s: MEM: Init ... !!!
    [C6x_2 ]      4.436602 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes!
    [C6x_2 ]      4.436621 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_2 ]      4.436638 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 byte!
    [C6x_2 ]      4.436655 s: MEM: Init ... Done !!!
    [C6x_2 ]      4.436664 s: IPC: Init ... !!!
    [C6x_2 ]      4.436679 s: IPC: 6 CPUs participating in IPC !!!
    [C6x_2 ]      4.436694 s: IPC: Waiting for HLOS to be ready ... !!!
    [C6x_2 ]     12.728464 s: IPC: HLOS is ready !!!
    [C6x_2 ]     12.751679 s: IPC: Init ... Done !!!
    [C6x_2 ]     12.751716 s: APP: Syncing with 5 CPUs ... !!!
    [C6x_2 ]     13.991263 s: APP: Syncing with 5 CPUs ... Done !!!
    [C6x_2 ]     13.991279 s: REMOTE_SERVICE: Init ... !!!
    [C6x_2 ]     13.992103 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_2 ]     13.992166 s:  VX_ZONE_INIT:Enabled
    [C6x_2 ]     13.992180 s:  VX_ZONE_ERROR:Enabled
    [C6x_2 ]     13.992191 s:  VX_ZONE_WARNING:Enabled
    [C6x_2 ]     13.993445 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_2 ]     13.993464 s: APP: OpenVX Target kernel init ... !!!
    [C6x_2 ]     13.993865 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_2 ]     13.993886 s: UDMA Copy: Init ... !!!
    [C6x_2 ]     14.015556 s: UDMA Copy: Init ... Done !!!
    [C6x_2 ]     14.015579 s: APP: Init ... Done !!!
    [C6x_2 ]     14.024051 s: APP: Run ... !!!
    [C6x_2 ]     14.024070 s: IPC: Starting echo test ...
    [C6x_2 ]     14.025621 s: APP: Run ... Done !!!
    [C6x_2 ]     14.026183 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[.] C66X_1[P] C66X_2[s] C7X_1[.]
    [C6x_2 ]     14.026243 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[.] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]     14.026300 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]     14.240533 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
    [C7x_1 ]      4.477741 s: CIO: Init ... Done !!!
    [C7x_1 ]      4.477767 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [C7x_1 ]      4.477784 s: APP: Init ... !!!
    [C7x_1 ]      4.477792 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      4.478976 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
    [C7x_1 ]      4.478992 s: SCICLIENT: DMSC FW revision 0x14
    [C7x_1 ]      4.479002 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_1 ]      4.479013 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      4.479023 s: UDMA: Init ... !!!
    [C7x_1 ]      4.488473 s: UDMA: Init ... Done !!!
    [C7x_1 ]      4.488485 s: MEM: Init ... !!!
    [C7x_1 ]      4.488496 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 byte!
    [C7x_1 ]      4.488518 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
    [C7x_1 ]      4.488535 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
    [C7x_1 ]      4.488553 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
    [C7x_1 ]      4.488570 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 byt!
    [C7x_1 ]      4.488588 s: MEM: Init ... Done !!!
    [C7x_1 ]      4.488597 s: IPC: Init ... !!!
    [C7x_1 ]      4.488607 s: IPC: 6 CPUs participating in IPC !!!
    [C7x_1 ]      4.488621 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_1 ]     13.023116 s: IPC: HLOS is ready !!!
    [C7x_1 ]     13.033579 s: IPC: Init ... Done !!!
    [C7x_1 ]     13.033595 s: APP: Syncing with 5 CPUs ... !!!
    [C7x_1 ]     13.991265 s: APP: Syncing with 5 CPUs ... Done !!!
    [C7x_1 ]     13.991284 s: REMOTE_SERVICE: Init ... !!!
    [C7x_1 ]     13.991552 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_1 ]     13.991578 s:  VX_ZONE_INIT:Enabled
    [C7x_1 ]     13.991589 s:  VX_ZONE_ERROR:Enabled
    [C7x_1 ]     13.991599 s:  VX_ZONE_WARNING:Enabled
    [C7x_1 ]     13.991849 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C7x_1 ]     13.991865 s: APP: OpenVX Target kernel init ... !!!
    [C7x_1 ]     13.991999 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_1 ]     13.992016 s: APP: Init ... Done !!!
    [C7x_1 ]     13.992027 s: APP: Run ... !!!
    [C7x_1 ]     13.992035 s: IPC: Starting echo test ...
    [C7x_1 ]     13.992533 s: APP: Run ... Done !!!
    [C7x_1 ]     14.022719 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[x] C66X_2[x] C7X_1[s]
    [C7x_1 ]     14.024866 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[x] C7X_1[s]
    [C7x_1 ]     14.026081 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
    [C7x_1 ]     14.240590 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
    
    

  • Hi Hao,

    The change you have made to enable PHY (by changing revision id in existing PHY driver code) is incorrect.

    You need to add your own PHY driver in case your PHY needs any extra config which is not available via standard PHY MII registers.

    If not, a generic PHY driver which gets selected if no dedicated driver is available should suffice.

    Can you please revert revision id update change and retry?

    Confirm you get link up with the generic PHY driver.

    Once we get link with it, you can share CPSW statistics (can be dumped using gel files) so we can look for any possible errors due to missing timing configuration if any.

  • Hi Prasad,

    We get link up with the phy driver with the log showing that 

    [MCU2_0]     14.045997 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'generic' : OK

    [MCU2_0]     14.046328 s: PHY 0 is alive
    [MCU2_0]     14.046416 s: PHY 1 is alive
    [MCU2_0]     14.046499 s: PHY 2 is alive
    Besides, I attached the CPSW 9G Stats below , hope it would be helpful for faster debugging.
    MAIN_Cortex_R5_0_0: GEL Output:           PORT0 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXGOODFRAMES              = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXBROADCASTFRAMES         = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXOCTETS                  = 0x0000014E
    MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES256T511        = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_0_NETOCTETS                 = 0x0000014E
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT1 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT2 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT3 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT4 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT5 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_TXGOODFRAMES              = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_TXBROADCASTFRAMES         = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_TXOCTETS                  = 0x0000014E
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_OCTETFRAMES256T511        = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_NETOCTETS                 = 0x0000014E
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_TX_PRI_REG             [0]= 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: STAT_5_TX_PRI_BCNT_REG        [0]= 0x0000014E
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT6 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT7 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:           PORT8 STATS         
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
    Regards

  • Hi Hao,

    Statistics shows that packets are being transmitted. I don't see any RX statistics. Are you sending anything from PC? 

    Also can you please connect wireshark and see packet transmitted from the TDA is seen.

    I believe there is a configuration issue in PHY which is causing packet being dropped in the PHY. 

  • Hi Prasad,

    We applied CCS to see the RX statistics of PHY, the result is that the phy register can recv packages from PC, but as you stated, no data package is received by CPSW. Furthermore, we need to locate where the configuration is wrong, and cause the unconnection.

    it would be appreciated if you could provide 1. the way that the package can be transimitted from cpsw to phy, 2. all the port we used is in RGMII mode, we wonder if the SGMII status is helpful anymore for checking out the port status.

    Rgds

  • Hello,

    user6477391 said:
    1. the way that the package can be transimitted from cpsw to phy,

    The EthFw runs DHCP server by default which sends DHCP request packets periodically. As you can see in the stats, host port RX (STAT_0_RXGOODFRAMES) which is packets transmitted by host is 1 meaning one packet was sent out. Also TX count for MAC port is 1 (STAT_5_TXGOODFRAMES ) which means CPSW sent that packet out.

    user6477391 said:
    2. all the port we used is in RGMII mode, we wonder if the SGMII status is helpful anymore for checking out the port status.

    I don't think this would be useful.

    I suspect issue to be PHY configuration or pinmux/PAD configuration. 

    You can probe the RGMII PADs between SOC and PHY to see any toggles. Confirm both RX and TX clocks are present and running at 125MHz.

    Also make sure your PHY is integrated correctly.

    software-dl.ti.com/.../enetphy_guide_top.html

  • Hi Prasad,

    Thanks for your advice, We have checked the related registers and the result is  that

    1. PHY can received the data from PC, the recv counter increased.

    2. The configuration of pinmux is right, but we confused of the RGMII4_RX_CTL and RGMII4_RXCLK configuration, which are 0x00050004, what value they should be.

    3.We also doubt that if the cpsw is sending data packages to phy in port 5, how we can double check that besides print the cpsw status.

    with regards 

  • Hi,

    user6477391 said:

    1. PHY can received the data from PC, the recv counter increased.

    OK. This should be good for confirming PHY RX status. You can also check PHY error registers for any errors.

    user6477391 said:

    2. The configuration of pinmux is right, but we confused of the RGMII4_RX_CTL and RGMII4_RXCLK configuration, which are 0x00050004, what value they should be.

    I see statistics incrementing for MAC PORT 5 but you are mentioning the RGMII4_RX_CTL, shouldn't it be RGMII5_RX_CTL?

    user6477391 said:

    3.We also doubt that if the cpsw is sending data packages to phy in port 5, how we can double check that besides print the cpsw status.

    Statistics registers and probing on signal lines are two ways I can think for confirming the data movement. 

  • Hi Prasad,

    Now, we move step forward by changing some codes for supporting our customed board. currently, we ping PC from TDA4 board, and showing status by using wireshark:

    the result shows that PC can receive data packages and make response.

    Also. we probe on signal line, CLK、RXDV、RXD0 for RGMII are all right when PC send data packages to TDA4, but MAC can not receive any data from PC.

    And the Cpsw status is below,

    For mac port 4,  we doubt if the port mask and rx_crc would affect the recv function of cpsw; or what could we do to solve the cpsw recv failure.

    Rgs

  • This is goood! Packets are being transmitted and received by CPSW.

    The issue you are not able to receive packets in your application is due to CRC errors.

    Normally CRC errors happen due to timing when RGMII delays are not configured correctly. As per spec, there should be 2.5ns delay between clock and data lines. 

    CPSW doesn't support configuring the RX (PHY TX) delay. You need to find out delay register in PHY data sheet and enable TX delay.

    Note CPSW TX delay is enabled (using RGMII_ID field in ENET1/2/_CTRL register so you dont need to change any config for TX (PHY RX) inside PHY.

  • Hi Prasad,

    Thanks for your advice, it truly solves the problem.

    Now, the Eth driver works, thank you so much.