TDA2HG: How to configure DSS Vout1 data reading clock edge

Part Number: TDA2HG

Hi,

From UB933's datasheet, it require data latched on the rising edge of the PCLK on default setting. Since we connect DSS vout1 to UB933,  I configure "DISPC_POL_FREQ0[14] IPC = 0 and CTRL_CORE_SMA_SW_1[19]DSS_CH0_IPC = 0"

root@dra7xx-evm:~# devmem2 0x4A002534
/dev/mem opened.
Memory mapped at address 0xb6fc4000.
Read at address  0x4A002534 (0xb6fc4534): 0x06000000
root@dra7xx-evm:~# devmem2 0x5800106C
/dev/mem opened.
Memory mapped at address 0xb6fc7000.
Read at address  0x5800106C (0xb6fc706c): 0x00003000

But from oscilloscope it seems still read data on falling edge.

So, did I miss something?

Thanks for your help!

BR/Tim