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Hello All,
I need help setting up circular buffer using EDMA3 and Mcasp.
I went through the PSP drivers and finding diffculty in setting up circular buffer.
Please help me stting up Mcasp & EDMA3 with out PSP drivers.
Back Ground:
we have 6713 application to be ported to 6747.
Tha application setup to have several transmit and recevie channels independenty which receives the 512bytes.
Thanks,
Sudheer Thota
Sudheer,
Do you need help setting up the McASP? It sounds like you already have the settings for the McASP from your previous application? I am working on a Chip Support Library (CSL) based example of the McASP, however it doesn't use the EDMA3. I can provide the McASP settings that I have, however the settings are largely dependent on the CODEC that is choosen. Can you provide more information on that?
Drew
Previous 6713 application is on CSL based MCBSP & EDMA.
I couldn't able to modify internals of PSP Based MCASP EDMA w.r.t CSL.
Sudheer,
Yeah, I'm pretty sure the Platform Support Package examples were developed on top of DSP/BIOS or SYS/BIOS, I'm not sure which on exactly. The driver user guide in the PSP should have some description of which BIOS package they used.
I wouldn't expect the PSP drivers to make heavy use of the CSL, although they might call CSL macros for peripheral initialization in the BIOS init functions. If you are not familiar with BIOS, jumping from the CSL takes a little bit of elbow grease.
As of right now, I'm not aware of any examples that make use of the EDMA3 that sit on top of CSL for 6747, however as I stated before we will be releasing a McASP example in the quickStart OMAP-L1x Package that you may reference for C6747. I don't have an exact date for you, but it should be available within the next two weeks.
Hello Drew,
could you please provide me an example PSP MCASP driver usage to provide application call back ?
Thanks in advance
Sudheer,
I'm not to familiar with the PSP code, so I'm not sure if this will suit your needs or not, however please see the link to the BIOS Platform Support Package. It's written on top of the C6748, but since the DSP Mega Module is the same, it should be straight forward to port it to the C6747.
Hi Drew,
I already using the same packges you mentioned.
Our requirement is to implement circular buffer using MCASP and EDMA3.
To avoid too many changes i would like to follow the same strcuturing from the existing application. This demand the CSLR MCASP usage with EDMA3.
Another Issue: Not able to get Application callback from SIO interface for MCASP & EDMA3.
Thanks
Sudheer Thota
Sudheer,
Thanks for the information.
Could you be more specific about application callback issues. If you can be specific about exactly what problems are you experiencing with BIOS SIO interface? Do you get an errors from BIOS? Do you get an empty buffer back?
Hello Drew
Finally this is what i cameup with. I tried lot of of ways. Before bigining with the ways i tried let be give you breif overview on my requirement.
we have large circular buffer of 4096 bytes and in each EDAM transfer we need to rerive 1 block of 512 bytes(total 8blocks = 4096). on each block receive we will notify the application on new data availbility. Mean time we also need to have TX channels configure to operate on the same buffer to trnasmit balocks continously.
Now the methods i Tried:
1) Started with ISSUE/Reclaim : Doesn't worked for more than 4 bufs.(Dont know the reason)
2) Low level MCASP/EDMA3 : Didn't woked.
3) Finally This is my last hope: MCASP with EDMA3 Driver
Configured MCASP Lowlevel intilization for free running.
Using the sample EDMA3LLD INIT
Crated 8 RX channles(7 link channels) with Callback
Created 8 Tx Channles(No Callback): To run freeely.
Issue here is is Edma Call back is not hitting and doesn't know how to debug.
Here are the setting i'm using:
MCASP:
/*-------------------------------------------------------------------------
Initialize MCASP0
-------------------------------------------------------------------------*/
mcasp0Regs->GBLCTL = 0; /* Reset */
mcasp0Regs->RGBLCTL = 0; /* Reset RX */
mcasp0Regs->XGBLCTL = 0; /* Reset TX */
mcasp0Regs->RSVD0[0] = 1; /* Free-running */
/*-------------------------------------------------------------------------
RX
-------------------------------------------------------------------------*/
mcasp0Regs->RMASK = 0xFFFFFFFF; // No padding used
mcasp0Regs->RFMT = 0x000080F0; // MSB 32bit, 0-delay, no pad, CFGBus
mcasp0Regs->AFSRCTL = 0x00000110; // 2TDM, 1bit Rising, INTERNAL FS, word
mcasp0Regs->ACLKRCTL = 0x00000080; // Rising INTERNAL CLK,(from tx side)
mcasp0Regs->AHCLKRCTL = 0x00000000; // AUX clk = 24. AHCLKR = 12.288
mcasp0Regs->RTDM = 0x00000003; // Slots 0,1
mcasp0Regs->RINTCTL = 0x00000000; // Not used
mcasp0Regs->RCLKCHK = 0x00000000; // 255-MAX 0-MIN, div-by-256
/*-------------------------------------------------------------------------
TX
-------------------------------------------------------------------------*/
mcasp0Regs->XMASK = 0xFFFFFFFF; // No padding used
mcasp0Regs->XFMT = 0x000080F0; // MSB 32bit, 0-delay, no pad, CFGBus
mcasp0Regs->AFSXCTL = 0x00000110; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp0Regs->ACLKXCTL = 0x000000C0; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp0Regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp0Regs->XTDM = 0x00000003; // Slots 0,1
mcasp0Regs->XINTCTL = 0x00000000; // Not used
mcasp0Regs->XCLKCHK = 0x00000000; // 255-MAX 0-MIN, div-by-256
mcasp0Regs->SRCTL7 = 0x000D; // MCASP1.AXR1[7] --> DIN
mcasp0Regs->SRCTL1 = 0x000E; // MCASP1.AXR1[1] <-- DOUT
mcasp0Regs->PFUNC = 0; // All MCASPs
mcasp0Regs->PDIR = 0x00000080; // All inputs except AXR0[7]
mcasp0Regs->DITCTL = 0x00000000; // Not used
mcasp0Regs->DLBCTL = 0x00000000; // Not used
mcasp0Regs->AMUTE = 0x00000000; // Not used
// Starting sections of the McASP
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XHCLKRST_MASK; // HS Clk
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XHCLKRST_MASK ) != CSL_MCASP_GBLCTL_XHCLKRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RHCLKRST_MASK; // HS Clk
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RHCLKRST_MASK ) != CSL_MCASP_GBLCTL_RHCLKRST_MASK );
#if 0
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XCLKRST_MASK; // Clk
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XCLKRST_MASK ) != CSL_MCASP_GBLCTL_XCLKRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RCLKRST_MASK; // Clk
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RCLKRST_MASK ) != CSL_MCASP_GBLCTL_RCLKRST_MASK );
#endif
mcasp0Regs->XSTAT = 0x0000ffff; // Clear all
mcasp0Regs->RSTAT = 0x0000ffff; // Clear all
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XSRCLR_MASK; // Serialize
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XSRCLR_MASK ) != CSL_MCASP_GBLCTL_XSRCLR_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RSRCLR_MASK; // Serialize
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RSRCLR_MASK ) != CSL_MCASP_GBLCTL_RSRCLR_MASK );
// Write a 0, so that no underrun occurs after releasing the state machine
mcasp0Regs->XBUF7 = 0;
mcasp0Regs->RBUF1 = 0;
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XSMRST_MASK; // State Machine
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XSMRST_MASK ) != CSL_MCASP_GBLCTL_XSMRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RSMRST_MASK; // State Machine
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RSMRST_MASK ) != CSL_MCASP_GBLCTL_RSMRST_MASK );
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XFRST_MASK; // Frame Sync
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XFRST_MASK ) != CSL_MCASP_GBLCTL_XFRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RFRST_MASK; // Frame Sync
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RFRST_MASK ) != CSL_MCASP_GBLCTL_RFRST_MASK );
EDMA:
void configTxBuffer(EDMA3_DRV_Handle hEdma, Uint32 chID, Uint32 tcc, Uint32 *dmaSrc, Uint32 sample_size, Uint32 sample_count)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)dmaSrc;
paramSet.destAddr = CSL_MCASP_0_DATA_REGS;
paramSet.srcBIdx = (Uint16)sample_size;
paramSet.destBIdx = 0;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.aCnt = (Uint16)sample_size;
paramSet.bCnt = (Uint16)sample_count;
paramSet.cCnt = 1;
/* For AB-synchronized transfers, BCNTRLD is not used. */
paramSet.bCntReload = (Uint16)sample_count;
paramSet.linkAddr = 0xFFFFu;
/* Set EDMA3_DRV_OPT_FIELD_TCINTEN to TRUE */
paramSet.opt |= (1 << CSL_EDMA3CC_OPT_TCINTEN_SHIFT);
/* Program the TCC */
paramSet.opt |= ((tcc << CSL_EDMA3CC_OPT_TCC_SHIFT) & CSL_EDMA3CC_OPT_TCC_MASK);
/* FIFO width is 32 bit */
paramSet.opt &= (0xFFFFF8FFu);
paramSet.opt |= (0x00000200u);
/* EDMA3_DRV_SYNC_A */
paramSet.opt &= (0xFFFFFFFB);
/* Src INCR & Dest CNST modes */
paramSet.opt &= (0xFFFFFFFE);
paramSet.opt |= (0x00000002);
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM (hEdma, chID, ¶mSet);
}
// Rx Interrupt flags - single interrupt handdler passs in a flag to
// identify the cause/Block of the interrupt.
Uint32 gRxBlock0tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock1tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock2tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock3tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock4tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock5tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock6tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock7tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock8tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock9tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock0tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock1tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock2tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock3tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock4tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock5tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock6tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock7tcc = EDMA3_DRV_TCC_ANY;
// handles for the DMA linked list on Rx side
Uint32 RcvChID = NULL;
Uint32 ReloadRcvBlock0ChID = CSL_EDMA3_CHA_MCASP0_RX;
Uint32 ReloadRcvBlock1ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock2ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock3ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock4ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock5ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock6ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock7ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock8ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock9ChID = EDMA3_DRV_LINK_CHANNEL;
// handles for the DMA linked list on TX side
Uint32 TxChID;
Uint32 ReloadTxBlock0ChID = CSL_EDMA3_CHA_MCASP0_TX;
Uint32 ReloadTxBlock1ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock2ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock3ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock4ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock5ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock6ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock7ChID = EDMA3_DRV_LINK_CHANNEL;
extern EDMA3_DRV_Handle hEdma;
EDMA3_RM_EventQueue queueNum = 0;
Int32 status = IOM_COMPLETED;
Uint32 numSamplesToDelay = 512;
EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS,
EDMA3_DRV_ITCCHEN_DIS,
EDMA3_DRV_TCINTEN_DIS,
EDMA3_DRV_ITCINTEN_DIS};
/* numSamplesToDelay = getNumSamplesToDelay(configTbl->eAudioDelay,configTbl->eAudioType, configTbl->cParamTwo); */
/* For receive use EDMA Queue 1 and for transmit use EDMA queue 0 */
queueNum = (EDMA3_RM_EventQueue)0;
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock0ChID,
&gRxBlock0tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock0tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock1ChID,
&gRxBlock1tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock1tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock2ChID,
&gRxBlock2tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock2tcc);
#if 0
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock3ChID,
&gRxBlock3tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock3tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock4ChID,
&gRxBlock4tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock4tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock5ChID,
&gRxBlock5tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock5tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock6ChID,
&gRxBlock6tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock6tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock7ChID,
&gRxBlock7tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock7tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock8ChID,
&gRxBlock8tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock8tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock9ChID,
&gRxBlock9tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock9tcc);
#endif
configRxBuffer(hEdma, ReloadRcvBlock0ChID, gRxBlock0tcc, gRxBuffer, BYTES_PER_SAMPLE, numSamplesToDelay);
configRxBuffer(hEdma, ReloadRcvBlock1ChID, gRxBlock1tcc, &gRxBuffer[numSamplesToDelay], BYTES_PER_SAMPLE, (4096 - numSamplesToDelay)); // 2048 elements complete here
configRxBuffer(hEdma, ReloadRcvBlock2ChID, gRxBlock2tcc, gRxBuffer, BYTES_PER_SAMPLE, NUM_RX_BLOCK2_ELEMENTS); // start at beginning
// configRxBuffer(hEdma, ReloadRcvBlock3ChID, gRxBlock3tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK3_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock4ChID, gRxBlock4tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK4_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock5ChID, gRxBlock5tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK5_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock6ChID, gRxBlock6tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK6_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock7ChID, gRxBlock7tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK7_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock8ChID, gRxBlock8tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS+ NUM_RX_BLOCK7_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK8_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock9ChID, gRxBlock9tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS+ NUM_RX_BLOCK7_ELEMENTS+ NUM_RX_BLOCK8_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK9_ELEMENTS);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock0ChID, ReloadRcvBlock1ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock1ChID, ReloadRcvBlock2ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock2ChID, ReloadRcvBlock1ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock3ChID, ReloadRcvBlock4ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock4ChID, ReloadRcvBlock5ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock5ChID, ReloadRcvBlock6ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock6ChID, ReloadRcvBlock7ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock7ChID, ReloadRcvBlock8ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock8ChID, ReloadRcvBlock9ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock9ChID, ReloadRcvBlock2ChID);
return status;
}
Int32 Mcasp0TxEdmaSetup(void)
{
extern EDMA3_DRV_Handle hEdma;
EDMA3_RM_EventQueue queueNum = 0;
Int32 status = IOM_COMPLETED;
/* numSamplesToDelay = getNumSamplesToDelay(configTbl->eAudioDelay,configTbl->eAudioType, configTbl->cParamTwo); */
/* For receive use EDMA Queue 1 and for transmit use EDMA queue 0 */
queueNum = (EDMA3_RM_EventQueue)1;
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock0ChID,
&gRxBlock0tcc,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock1ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock2ChID,
NULL,
queueNum,
NULL,
NULL);
#if 0
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock3ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock4ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock5ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock6ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock7ChID,
NULL,
queueNum,
NULL,
NULL);
#endif
configTxBuffer(hEdma, ReloadTxBlock0ChID, gTxBlock0tcc, gRxBuffer, BYTES_PER_SAMPLE, NUM_TX_BLOCK0_ELEMENTS);
configTxBuffer(hEdma, ReloadTxBlock1ChID, gTxBlock1tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK1_ELEMENTS);
configTxBuffer(hEdma, ReloadTxBlock2ChID, gTxBlock2tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK2_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock3ChID, gTxBlock3tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK3_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock4ChID, gTxBlock4tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS + NUM_TX_BLOCK3_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK4_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock5ChID, gTxBlock5tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS + NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK5_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock6ChID, gTxBlock6tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS+ NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS + NUM_TX_BLOCK5_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK6_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock7ChID, gTxBlock7tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS+ NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS + NUM_TX_BLOCK5_ELEMENTS + NUM_TX_BLOCK6_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK7_ELEMENTS);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock0ChID, ReloadTxBlock1ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock1ChID, ReloadTxBlock2ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock2ChID, ReloadTxBlock3ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock3ChID, ReloadTxBlock4ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock4ChID, ReloadTxBlock5ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock5ChID, ReloadTxBlock6ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock6ChID, ReloadTxBlock7ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock7ChID, ReloadTxBlock0ChID);
return status;
}
void edma_setup(void)
{
extern EDMA3_DRV_Handle hEdma;
Mcasp0RxEdmaSetup();
printf("Im here");
Mcasp0TxEdmaSetup();
//EDMA3_DRV_enableTransfer (hEdma, ReloadTxBlock0ChID, EDMA3_DRV_TRIG_MODE_EVENT);
EDMA3_DRV_enableTransfer (hEdma, ReloadRcvBlock0ChID, EDMA3_DRV_TRIG_MODE_EVENT);
}
Thanks
Sudheer Thota
Thanks
Hello Drew
Finally this is what i cameup with. I tried lot of of ways. Before bigining with the ways i tried let be give you breif overview on my requirement.
we have large circular buffer of 4096 bytes and in each EDAM transfer we need to rerive 1 block of 512 bytes(total 8blocks = 4096). on each block receive we will notify the application on new data availbility. Mean time we also need to have TX channels configure to operate on the same buffer to trnasmit balocks continously.
Now the methods i Tried:
1) Started with ISSUE/Reclaim : Doesn't worked for more than 4 bufs.(Dont know the reason)
2) Low level MCASP/EDMA3 : Didn't woked.
3) Finally This is my last hope: MCASP with EDMA3 Driver
Configured MCASP Lowlevel intilization for free running.
Using the sample EDMA3LLD INIT
Crated 8 RX channles(7 link channels) with Callback
Created 8 Tx Channles(No Callback): To run freeely.
Issue here is is Edma Call back is not hitting and doesn't know how to debug.
Here are the setting i'm using:
MCASP:
/*-------------------------------------------------------------------------
Initialize MCASP0
-------------------------------------------------------------------------*/
mcasp0Regs->GBLCTL = 0; /* Reset */
mcasp0Regs->RGBLCTL = 0; /* Reset RX */
mcasp0Regs->XGBLCTL = 0; /* Reset TX */
mcasp0Regs->RSVD0[0] = 1; /* Free-running */
/*-------------------------------------------------------------------------
RX
-------------------------------------------------------------------------*/
mcasp0Regs->RMASK = 0xFFFFFFFF; // No padding used
mcasp0Regs->RFMT = 0x000080F0; // MSB 32bit, 0-delay, no pad, CFGBus
mcasp0Regs->AFSRCTL = 0x00000110; // 2TDM, 1bit Rising, INTERNAL FS, word
mcasp0Regs->ACLKRCTL = 0x00000080; // Rising INTERNAL CLK,(from tx side)
mcasp0Regs->AHCLKRCTL = 0x00000000; // AUX clk = 24. AHCLKR = 12.288
mcasp0Regs->RTDM = 0x00000003; // Slots 0,1
mcasp0Regs->RINTCTL = 0x00000000; // Not used
mcasp0Regs->RCLKCHK = 0x00000000; // 255-MAX 0-MIN, div-by-256
/*-------------------------------------------------------------------------
TX
-------------------------------------------------------------------------*/
mcasp0Regs->XMASK = 0xFFFFFFFF; // No padding used
mcasp0Regs->XFMT = 0x000080F0; // MSB 32bit, 0-delay, no pad, CFGBus
mcasp0Regs->AFSXCTL = 0x00000110; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp0Regs->ACLKXCTL = 0x000000C0; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp0Regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp0Regs->XTDM = 0x00000003; // Slots 0,1
mcasp0Regs->XINTCTL = 0x00000000; // Not used
mcasp0Regs->XCLKCHK = 0x00000000; // 255-MAX 0-MIN, div-by-256
mcasp0Regs->SRCTL7 = 0x000D; // MCASP1.AXR1[7] --> DIN
mcasp0Regs->SRCTL1 = 0x000E; // MCASP1.AXR1[1] <-- DOUT
mcasp0Regs->PFUNC = 0; // All MCASPs
mcasp0Regs->PDIR = 0x00000080; // All inputs except AXR0[7]
mcasp0Regs->DITCTL = 0x00000000; // Not used
mcasp0Regs->DLBCTL = 0x00000000; // Not used
mcasp0Regs->AMUTE = 0x00000000; // Not used
// Starting sections of the McASP
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XHCLKRST_MASK; // HS Clk
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XHCLKRST_MASK ) != CSL_MCASP_GBLCTL_XHCLKRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RHCLKRST_MASK; // HS Clk
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RHCLKRST_MASK ) != CSL_MCASP_GBLCTL_RHCLKRST_MASK );
#if 0
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XCLKRST_MASK; // Clk
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XCLKRST_MASK ) != CSL_MCASP_GBLCTL_XCLKRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RCLKRST_MASK; // Clk
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RCLKRST_MASK ) != CSL_MCASP_GBLCTL_RCLKRST_MASK );
#endif
mcasp0Regs->XSTAT = 0x0000ffff; // Clear all
mcasp0Regs->RSTAT = 0x0000ffff; // Clear all
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XSRCLR_MASK; // Serialize
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XSRCLR_MASK ) != CSL_MCASP_GBLCTL_XSRCLR_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RSRCLR_MASK; // Serialize
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RSRCLR_MASK ) != CSL_MCASP_GBLCTL_RSRCLR_MASK );
// Write a 0, so that no underrun occurs after releasing the state machine
mcasp0Regs->XBUF7 = 0;
mcasp0Regs->RBUF1 = 0;
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XSMRST_MASK; // State Machine
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XSMRST_MASK ) != CSL_MCASP_GBLCTL_XSMRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RSMRST_MASK; // State Machine
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RSMRST_MASK ) != CSL_MCASP_GBLCTL_RSMRST_MASK );
mcasp0Regs->XGBLCTL |= CSL_MCASP_GBLCTL_XFRST_MASK; // Frame Sync
while ( ( mcasp0Regs->XGBLCTL & CSL_MCASP_GBLCTL_XFRST_MASK ) != CSL_MCASP_GBLCTL_XFRST_MASK );
mcasp0Regs->RGBLCTL |= CSL_MCASP_GBLCTL_RFRST_MASK; // Frame Sync
while ( ( mcasp0Regs->RGBLCTL & CSL_MCASP_GBLCTL_RFRST_MASK ) != CSL_MCASP_GBLCTL_RFRST_MASK );
EDMA:
void configTxBuffer(EDMA3_DRV_Handle hEdma, Uint32 chID, Uint32 tcc, Uint32 *dmaSrc, Uint32 sample_size, Uint32 sample_count)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)dmaSrc;
paramSet.destAddr = CSL_MCASP_0_DATA_REGS;
paramSet.srcBIdx = (Uint16)sample_size;
paramSet.destBIdx = 0;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.aCnt = (Uint16)sample_size;
paramSet.bCnt = (Uint16)sample_count;
paramSet.cCnt = 1;
/* For AB-synchronized transfers, BCNTRLD is not used. */
paramSet.bCntReload = (Uint16)sample_count;
paramSet.linkAddr = 0xFFFFu;
/* Set EDMA3_DRV_OPT_FIELD_TCINTEN to TRUE */
paramSet.opt |= (1 << CSL_EDMA3CC_OPT_TCINTEN_SHIFT);
/* Program the TCC */
paramSet.opt |= ((tcc << CSL_EDMA3CC_OPT_TCC_SHIFT) & CSL_EDMA3CC_OPT_TCC_MASK);
/* FIFO width is 32 bit */
paramSet.opt &= (0xFFFFF8FFu);
paramSet.opt |= (0x00000200u);
/* EDMA3_DRV_SYNC_A */
paramSet.opt &= (0xFFFFFFFB);
/* Src INCR & Dest CNST modes */
paramSet.opt &= (0xFFFFFFFE);
paramSet.opt |= (0x00000002);
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM (hEdma, chID, ¶mSet);
}
// Rx Interrupt flags - single interrupt handdler passs in a flag to
// identify the cause/Block of the interrupt.
Uint32 gRxBlock0tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock1tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock2tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock3tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock4tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock5tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock6tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock7tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock8tcc = EDMA3_DRV_TCC_ANY;
Uint32 gRxBlock9tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock0tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock1tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock2tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock3tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock4tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock5tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock6tcc = EDMA3_DRV_TCC_ANY;
Uint32 gTxBlock7tcc = EDMA3_DRV_TCC_ANY;
// handles for the DMA linked list on Rx side
Uint32 RcvChID = NULL;
Uint32 ReloadRcvBlock0ChID = CSL_EDMA3_CHA_MCASP0_RX;
Uint32 ReloadRcvBlock1ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock2ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock3ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock4ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock5ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock6ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock7ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock8ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadRcvBlock9ChID = EDMA3_DRV_LINK_CHANNEL;
// handles for the DMA linked list on TX side
Uint32 TxChID;
Uint32 ReloadTxBlock0ChID = CSL_EDMA3_CHA_MCASP0_TX;
Uint32 ReloadTxBlock1ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock2ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock3ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock4ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock5ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock6ChID = EDMA3_DRV_LINK_CHANNEL;
Uint32 ReloadTxBlock7ChID = EDMA3_DRV_LINK_CHANNEL;
extern EDMA3_DRV_Handle hEdma;
EDMA3_RM_EventQueue queueNum = 0;
Int32 status = IOM_COMPLETED;
Uint32 numSamplesToDelay = 512;
EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS,
EDMA3_DRV_ITCCHEN_DIS,
EDMA3_DRV_TCINTEN_DIS,
EDMA3_DRV_ITCINTEN_DIS};
/* numSamplesToDelay = getNumSamplesToDelay(configTbl->eAudioDelay,configTbl->eAudioType, configTbl->cParamTwo); */
/* For receive use EDMA Queue 1 and for transmit use EDMA queue 0 */
queueNum = (EDMA3_RM_EventQueue)0;
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock0ChID,
&gRxBlock0tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock0tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock1ChID,
&gRxBlock1tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock1tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock2ChID,
&gRxBlock2tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock2tcc);
#if 0
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock3ChID,
&gRxBlock3tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock3tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock4ChID,
&gRxBlock4tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock4tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock5ChID,
&gRxBlock5tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock5tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock6ChID,
&gRxBlock6tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock6tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock7ChID,
&gRxBlock7tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock7tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock8ChID,
&gRxBlock8tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock8tcc);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadRcvBlock9ChID,
&gRxBlock9tcc,
queueNum,
&McaspEdmaCallback,
&gRxBlock9tcc);
#endif
configRxBuffer(hEdma, ReloadRcvBlock0ChID, gRxBlock0tcc, gRxBuffer, BYTES_PER_SAMPLE, numSamplesToDelay);
configRxBuffer(hEdma, ReloadRcvBlock1ChID, gRxBlock1tcc, &gRxBuffer[numSamplesToDelay], BYTES_PER_SAMPLE, (4096 - numSamplesToDelay)); // 2048 elements complete here
configRxBuffer(hEdma, ReloadRcvBlock2ChID, gRxBlock2tcc, gRxBuffer, BYTES_PER_SAMPLE, NUM_RX_BLOCK2_ELEMENTS); // start at beginning
// configRxBuffer(hEdma, ReloadRcvBlock3ChID, gRxBlock3tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK3_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock4ChID, gRxBlock4tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK4_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock5ChID, gRxBlock5tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK5_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock6ChID, gRxBlock6tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK6_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock7ChID, gRxBlock7tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK7_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock8ChID, gRxBlock8tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS+ NUM_RX_BLOCK7_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK8_ELEMENTS);
// configRxBuffer(hEdma, ReloadRcvBlock9ChID, gRxBlock9tcc, &gRxBuffer[NUM_RX_BLOCK2_ELEMENTS+ NUM_RX_BLOCK3_ELEMENTS+ NUM_RX_BLOCK4_ELEMENTS+ NUM_RX_BLOCK5_ELEMENTS+ NUM_RX_BLOCK6_ELEMENTS+ NUM_RX_BLOCK7_ELEMENTS+ NUM_RX_BLOCK8_ELEMENTS], BYTES_PER_SAMPLE, NUM_RX_BLOCK9_ELEMENTS);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock0ChID, ReloadRcvBlock1ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock1ChID, ReloadRcvBlock2ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock2ChID, ReloadRcvBlock1ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock3ChID, ReloadRcvBlock4ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock4ChID, ReloadRcvBlock5ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock5ChID, ReloadRcvBlock6ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock6ChID, ReloadRcvBlock7ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock7ChID, ReloadRcvBlock8ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock8ChID, ReloadRcvBlock9ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadRcvBlock9ChID, ReloadRcvBlock2ChID);
return status;
}
Int32 Mcasp0TxEdmaSetup(void)
{
extern EDMA3_DRV_Handle hEdma;
EDMA3_RM_EventQueue queueNum = 0;
Int32 status = IOM_COMPLETED;
/* numSamplesToDelay = getNumSamplesToDelay(configTbl->eAudioDelay,configTbl->eAudioType, configTbl->cParamTwo); */
/* For receive use EDMA Queue 1 and for transmit use EDMA queue 0 */
queueNum = (EDMA3_RM_EventQueue)1;
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock0ChID,
&gRxBlock0tcc,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock1ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock2ChID,
NULL,
queueNum,
NULL,
NULL);
#if 0
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock3ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock4ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock5ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock6ChID,
NULL,
queueNum,
NULL,
NULL);
status = EDMA3_DRV_requestChannel(hEdma,
&ReloadTxBlock7ChID,
NULL,
queueNum,
NULL,
NULL);
#endif
configTxBuffer(hEdma, ReloadTxBlock0ChID, gTxBlock0tcc, gRxBuffer, BYTES_PER_SAMPLE, NUM_TX_BLOCK0_ELEMENTS);
configTxBuffer(hEdma, ReloadTxBlock1ChID, gTxBlock1tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK1_ELEMENTS);
configTxBuffer(hEdma, ReloadTxBlock2ChID, gTxBlock2tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK2_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock3ChID, gTxBlock3tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK3_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock4ChID, gTxBlock4tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS + NUM_TX_BLOCK3_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK4_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock5ChID, gTxBlock5tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS + NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK5_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock6ChID, gTxBlock6tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS+ NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS + NUM_TX_BLOCK5_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK6_ELEMENTS);
// configTxBuffer(hEdma, ReloadTxBlock7ChID, gTxBlock7tcc, &gRxBuffer[NUM_TX_BLOCK0_ELEMENTS + NUM_TX_BLOCK1_ELEMENTS + NUM_TX_BLOCK2_ELEMENTS+ NUM_TX_BLOCK3_ELEMENTS+ NUM_TX_BLOCK4_ELEMENTS + NUM_TX_BLOCK5_ELEMENTS + NUM_TX_BLOCK6_ELEMENTS], BYTES_PER_SAMPLE, NUM_TX_BLOCK7_ELEMENTS);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock0ChID, ReloadTxBlock1ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock1ChID, ReloadTxBlock2ChID);
status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock2ChID, ReloadTxBlock3ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock3ChID, ReloadTxBlock4ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock4ChID, ReloadTxBlock5ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock5ChID, ReloadTxBlock6ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock6ChID, ReloadTxBlock7ChID);
// status = EDMA3_DRV_linkChannel (hEdma, ReloadTxBlock7ChID, ReloadTxBlock0ChID);
return status;
}
void edma_setup(void)
{
extern EDMA3_DRV_Handle hEdma;
Mcasp0RxEdmaSetup();
printf("Im here");
Mcasp0TxEdmaSetup();
//EDMA3_DRV_enableTransfer (hEdma, ReloadTxBlock0ChID, EDMA3_DRV_TRIG_MODE_EVENT);
EDMA3_DRV_enableTransfer (hEdma, ReloadRcvBlock0ChID, EDMA3_DRV_TRIG_MODE_EVENT);
}
Thanks
Sudheer Thota
Thanks
Sudheer,
sudheer thota said:1) Started with ISSUE/Reclaim : Doesn't worked for more than 4 bufs.(Dont know the reason)
I'm not aware of any restrictions on the number of buffers you can use with the SIO_ISSUE/RECLAIM model, but since this is a very typical use case for transporting data between McASP and CPU, it might be worth your time to investigate why your program doesn't work as the number of buffers increases beyond 4.
It looks like you are only using only two McASP serializers per your configuration. I'm not sure I fully understand why you would need 8 buffers to transport data two and from the McASP. I would think that 4 would suffice. (Two for Rx, Two for Tx) You use the buffers in a ping-pong style where you are processing one set of Rx/Tx buffers, while the other is being filled for incoming/outgoing Audio.
Is the audio supply running at such a high frequency that you need 8 buffers? Maybe there is some other constraint that I don't understand in your system.
Do you have the SIO attributes configured to handle more than two buffers in your BIOS configuration file? I believe the number of buffers defaults two two/stream as per the DSP/BIOS5 API Reference Guide. If you have two streams (Rx, and Tx) , this may be the reason why you can only get it to work with 4 buffers.
sudheer thota said:2) Low level MCASP/EDMA3 : Didn't woked.
What didn't work? Did you not get the McASP to generate an event to the EDMA3? Did the transfer not occur?
sudheer thota said:3) Finally This is my last hope: MCASP with EDMA3 Driver
I'm not familiar with the EDMA3 Low Level Drivers, but have you referenced the EMDA3 Low Level Driver Wiki Page?
Hello Drew,
I finally could able to tweak the mcasp driver and able to create 10 link channel and able to pass the audio.
Now the issues is i'm getting distorted output.
Do i need to maintain gap between buffer locations?
Thanks
Sudheer Thota
sudheer thota said:Do i need to maintain gap between buffer locations?
You shouldn't have to, but you'll have to review the McASP to driver to determine how it expects the buffers to be organized. Also, you may wish to check your McASP Format Unit settings to make sure you are not unintentionally masking off any bits / shifting the data wrong.
Hello Drew,
I succedded with the Ring buffer implementation.
Could you please guide me how i can get the Link param details from the EDMA3 Callback?(TCC is allways the Event Number for all link params)
This is neede for me to get the buffer indexes for notifying Application.
Thanks
Sudheer Thota
Sudheer,
I am not familiar with the EDMA Low Level Drivers, so unfortunately I won't be able to provide much support on this, however please refer to the EMDA3 LLD Wiki Article for suggestions. You may also find it useful to search the Forums for EDMA3 LLD Support.
Hi Sudheer,
I'm also doing the same kind of a work which you have dobne successfully but i have stucked in few things.
I want to use 8 channel to pass the audio using mcasp and edma driver. How you are maintaining the circular mechanism buffer so that you dont loose any packets.
regards
Suhasini
Hi Sushani,
I defined 4096 circular buffer to hold 8 512 blocks of (256L & 256 R).
Used param link tables to connect sequentially and at the end it link back to 0th location.Here is the code snippet
/* link this paramset with the main channel */
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->xferChan, chanHandle->pramTbl[0]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[0], chanHandle->pramTbl[1]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[1], chanHandle->pramTbl[2]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[2], chanHandle->pramTbl[3]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[3], chanHandle->pramTbl[4]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[4], chanHandle->pramTbl[5]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[5], chanHandle->pramTbl[6]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[6], chanHandle->pramTbl[7]);
EDMA3_DRV_linkChannel(chanHandle->edmaHandle, chanHandle->pramTbl[7], chanHandle->pramTbl[0]);
Hope this helps.
Sudheer
