PROCESSOR-SDK-DRA8X-TDA4X: Thermal shutdown alerts and interrupts

Dipti Natu

Part Number: PROCESSOR-SDK-DRA8X-TDA4X
Other Parts Discussed in Thread: SYSBIOS

Hello,

As per the suggestion provided in earlier query :

We went through the applications vtm_pvt_sensor_maxt_outrg, vtm_pvt_sensor_read and vtm_pvt_sensor_temp_alert .

We need an application that will provide some alert to the user once a particular threshold is reached and thermal shutdown begins. So in order to achieve that we used the vtm_pvt_sensor_temp_alert application provided and compiled it as a library for R5F-SYSBIOS. We used this library and linked this function to our existing application(runs dummy logic on all cores to increase the CPU utilization) using a remote service call.

Expectation : Monitoring alerts for particular thresholds in WKUP_VTM_TMPSENS_STAT registers and no interrupt should be enabled.

Note - The registration of all interrupts were disabled in the application. The alert in CSL_vtm_tsStat_val were monitored.

Observation : When this application is run, only the gt_th_alert bit goes high, although the threshold value is not reached. And then it remains high for the rest of the run.

So can only the alerts be enabled and interrupts be disabled ? Is there any specific requirement to do it.?

Thanks,

Dipti Natu

over 4 years ago

0 Keerthy J over 4 years ago

TI__Guru**** 164680 points

Hi Dipti,

The VTM Hardware mechanisms are enabled via interrupts. If you want to disable them
& still monitor thermal then the one option that i can think of is to do a polling every
Second or 2 second or 5 seconds based on your need. Basically pure software way
to poll the temperature periodically.

Hope i understood your question.

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

1. As I understand from your reply, the alerts can only be monitored through interrupts and not status flags.

2. Initially we had the interrupts enabled when we integrated the baremetal application provided with vision_apps which has Sysbios running on R5F. However the application hanged during the interrupt registration. So, we disabled interrupt registration and wanted to monitor alerts through status flags.

3. Can you help us register the interrupts from vision_apps (Sysbios R5F).

In addition to above we also tried to run the baremetal application on EVM using debugger. The application get loaded successfully, core enters running mode, but we cannot see any prints on UART console. We followed the PSDK user guide for debugging using CCS. What can be the issue..?

Thanks,

Dipti Natu

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Hi Dipti,

For the thermal alerts check this:

So as soon as the GT_TH1_INT fires you will need to take some cooling action otherwise that status will be set like how you have observed.

for TSHUT:

What is the behavior that you see when you hit the TSHUT temperature? Can you elaborate?

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

We have already gone through this details mentioned in TRM and also the example application provided in pdk_jacinto_07_00_00\packages\ti\csl\example\vtm\vtm_pvt_sensor_temp_alert which you had already mentioned in the previous response.

After going through the example, we integrated the example in vision_apps and were successful in compiling the application along with the vtm_pvt_sensor_temp_alert().

Following run time issues were faced :

1. The application hangs at run time : When debugged the application hangs only after registration of ISR is done using Osal_RegisterInterrupt() as given in the example. If this registration is disabled the code does not hang and gives the updated temperature values from temperature sensors.

2. Alert status in CSL_vtm_tsStat_val structure did not reflect any values : As a workaround to resolve the hang issue due to ISR registration, we decided to monitor the threshold alert status in CSL_vtm_tsStat_val structure. But we could see that even though the temperature exceeds the threshold set, the alert bits don't show any change.

As a result through various implementations and testing. There are no interrupts generated nor are the alert status updated.

So we also tried testing the example application provided in pdk_jacinto_07_00_00\packages\ti\csl\example\vtm\vtm_pvt_sensor_temp_alert : The application get loaded successfully, core enters running mode, but we cannot see any prints on UART console.

We would like to know if (i) Alert monitoring cannot be done without Interrupts..?

(ii) ISR registration in example code can be used when building the code for R5F SYSBIOS in vision apps and not as a baremetal application...? If no, can you suggest us a way to do it..?

Thanks,

Dipti Natu

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Hi Dipti,

I checked with the TI RTOS expert for thermal.

1. The application hangs at run time : When debugged the application hangs only after registration of ISR is done using Osal_RegisterInterrupt() as given in the example. If this registration is disabled the code does not hang and gives the updated temperature values from temperature sensors.

We have not seen any issues. RTOS drivers/examples are using this API and not seen any issues yet.
How are you registering the ISR? Has the Params Initialization called before the register interrupt OR did you
check if all the parameters are initialized? If you can give us the parameters used for Osal_RegisterInterrupt(),
we can plug in those values and check if there is any OSAL issue or something else.

Is the part having the correct EFUSE values for VTM? The example in CSL is setting the efuse values for mimicking for a given part. So you should not set the EFUSE. Please check the EFUSE register values. Also, Is the sensor programmed for continuous mode or single shot mode? It should be set to continuous mode for continuous monitoring of the temperature.

Is threshold enabled? Is the correct temperature sensor ID is used to get the values? You can use CSL_vtmTsGetThresholds() API to read the current threshold and enabled/disabled status for a given temperature sensor ID. As a test, can you read the temperature sensor values for all sensors and cross verify if the expected temperature changes are matching to a temperature sensor?

Note: I will be out for a week so responses will be delayed.

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

1. Please find the file for your reference :

Fullscreen vtm_sensor_temp_alert.c Download

/*
 *  Copyright (c) Texas Instruments Incorporated 2020
 *
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 *  modification, are permitted provided that the following conditions
 *  are met:
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     vtm_sensor_temp_alert.c
 *
 *  \brief    This file contains VTM PVT sensor thermal alert example application
 *            Implementation.
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "vtm_sensor_temp_alert.h"
//#define THR_DEBUG    //Define this to enable prints to debug threshold values...


#define CSL_VTM_TEST_NUM_EFUSE_REGS                              (4u)
#define CSL_VTM_TEST_EFUSE_BASE_ADDR                             (0x43000300UL)
#define CSL_VTM_TEST_NUM_SENSORS                                 (5u)
#define CSL_VTM_TEST_THERMAL_RST_MASK                            (1 << 24)

#if defined(SOC_J721E)
#define CSL_VTM_TEST_CFG1_BASE          (CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE)
#define CSL_VTM_TEST_CFG2_BASE          (CSL_WKUP_VTM0_MMR_VBUSP_CFG2_BASE)
#elif defined (SOC_AM64X)
#define CSL_VTM_TEST_CFG1_BASE          (CSL_VTM0_MMR_VBUSP_CFG1_BASE)
#define CSL_VTM_TEST_CFG2_BASE          (CSL_VTM0_MMR_VBUSP_CFG2_BASE)
#else
/* Address needs to be defined */
#endif


/* ========================================================================== */
/*                                Macros                                      */
/* ========================================================================== */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
volatile uint32_t g_efuse_0, gefuse_1, gefuse_2, gefuse_3;
volatile Bool     g_all_thr_alerts_fired = FALSE, g_lt_thr0_alert_fired = FALSE;
volatile Bool     g_gt_thr1_alert_fired = FALSE, g_gt_thr2_alert_fired = FALSE;
volatile int32_t  g_current_temp =0;
Bool gAuto_test = (Bool) TEST_THR_AUTO_TEST_FOR_RTOS_NIGHTLY;
HwiP_Handle       gHwiP_handle[4];

/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/* Unity functions */
//void test_csl_vtm_pvt_sensor_temp_alert_runner(void);
//void test_csl_vtm_pvt_sensor_temp_alert (void);

/* Threshold interrupt service routines */
void test_csl_vtm_pvt_sensor_ltThr0_isr(uintptr_t arg);
void test_csl_vtm_pvt_sensor_gtThr1_isr(uintptr_t arg);
void test_csl_vtm_pvt_sensor_gtThr2_isr(uintptr_t arg);
void test_csl_register_temp_thr_isrs(uintptr_t isr, uintptr_t arg, int32_t thr_code);
void test_csl_unregister_temp_thr_isrs(int32_t thr_code);
void test_csl_set_temp_thr(CSL_vtm_adc_code adc_code, CSL_vtm_tmpSens_id ts_id, int32_t thr_code);



/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

void test_csl_vtm_pvt_sensor_ltThr0_isr(uintptr_t arg)
{
    printf (" In function lt_thr0_isr \n");
    #if 1
    g_lt_thr0_alert_fired = TRUE;
    CSL_vtm_vdThr_interrupt_ctrl ctrl;

    /* Ack the interrupt, by clearing the pending bit */
    ctrl = (CSL_VTM_VD_LT_THR0_INTR_EN_CLR | \
            CSL_VTM_VD_GT_THR1_INTR_EN_SET | \
            CSL_VTM_VD_GT_THR2_INTR_EN_SET | \
            CSL_VTM_VD_LT_THR0_INTR_RAW_CLR | \
            CSL_VTM_VD_GT_THR1_INTR_RAW_CLR | \
            CSL_VTM_VD_GT_THR2_INTR_RAW_CLR);            
            
    CSL_vtmVdThrIntrCtrl((CSL_vtm_cfg1Regs *)CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE, \
                          CSL_VTM_VD_DOMAIN_1, ctrl, FALSE);

    printf (" \n\n\ngot ltThr0 interrupt \n");
    printf (" \nSystem at a temperature below the threshold of %d \nSystem running at a safe temperature \n", (int32_t) arg);
    #endif
}

void test_csl_vtm_pvt_sensor_gtThr1_isr(uintptr_t arg)
{
    printf (" In function gt_thr1_isr \n");
    #if 1
    g_gt_thr1_alert_fired = TRUE;
    CSL_vtm_vdThr_interrupt_ctrl ctrl;
    /*
    - disable the gt1 interrupt
    - clear the gt1 interrupt
    - clear the lt0 interrupt
    - enable the lt0 intterupt
    */
    ctrl = (CSL_VTM_VD_GT_THR1_INTR_EN_CLR  |  \
            CSL_VTM_VD_GT_THR1_INTR_RAW_CLR |  \
            CSL_VTM_VD_LT_THR0_INTR_EN_SET  |  \
            CSL_VTM_VD_LT_THR0_INTR_RAW_CLR);

    /* Ack and Re-enable the LT_THR0 interrupt to let system know if cooling took place */
    CSL_vtmVdThrIntrCtrl((CSL_vtm_cfg1Regs *)CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE, \
                          CSL_VTM_VD_DOMAIN_1, ctrl, FALSE);
    printf (" \n\n\ngot gtThr1 interrupt \n");
    printf (" \nCrossed threshold %d  System should take action to implement system cooling \n", (int32_t) arg);
    #endif
}

void test_csl_vtm_pvt_sensor_gtThr2_isr(uintptr_t arg)
{
    printf (" In function gt_thr2_isr \n");
    #if 1
    g_gt_thr2_alert_fired = TRUE;
    CSL_vtm_vdThr_interrupt_ctrl ctrl;
    /* Ack the interrupt, by clearing the pending bit */
    ctrl = (CSL_VTM_VD_GT_THR2_INTR_EN_CLR | \
            CSL_VTM_VD_GT_THR2_INTR_RAW_CLR);
    CSL_vtmVdThrIntrCtrl((CSL_vtm_cfg1Regs *)CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE, \
                              CSL_VTM_VD_DOMAIN_1, ctrl, FALSE);
    printf (" \n\n\ngot gtThr2 interrupt \n");
    printf (" \nCrossed threshold %d  System should take critical action to implement system cooling \n", (int32_t) arg);
    #endif
}

#ifdef UNITY_INCLUDE_CONFIG_H
/*
 *  ======== Unity set up and tear down ========
 */
void setUp(void)
{
    /* Do nothing */
}

void tearDown(void)
{
    /* Do nothing */
}
#endif

void test_csl_set_temp_thr(CSL_vtm_adc_code adc_code, CSL_vtm_tmpSens_id ts_id, int32_t thr_code)
{
    CSL_vtm_cfg1Regs         *p_cfg = (CSL_vtm_cfg1Regs *) CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE;
    CSL_vtm_tsThrVal         thr_val;
    CSL_vtm_vdThr_interrupt_ctrl  ctrl;
    CSL_vtm_vdEvt_sel_set   vd_temp_evts;
    #ifdef THR_DEBUG
    int32_t                 retVal = CSL_PASS;
    #endif
    

    switch (ts_id)
    {
        case CSL_VTM_TS_ID_0:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_0;
            break;
        case CSL_VTM_TS_ID_1:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_1;
            break;
        case CSL_VTM_TS_ID_2:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_2;
            break;
        case CSL_VTM_TS_ID_3:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_3;
            break;            
        case CSL_VTM_TS_ID_4:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_4;
            break;
        case CSL_VTM_TS_ID_5:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_5;
            break;
        case CSL_VTM_TS_ID_6:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_6;
            break;          
        case CSL_VTM_TS_ID_7:
        default:
            vd_temp_evts =  CSL_VTM_VD_EVT_SELECT_TEMP_SENSOR_7;
            break;            
    }

    /* Program VTM  enabling the gt1 and gt2 interrupts, but disabling the lt0_int */
    switch (thr_code)
    {
        case TEST_CSL_VTM_GT_THR2_SET:
            thr_val.thrValidMap = CSL_VTM_GT_TH2_VALID;
            thr_val.gtTh2En     = TRUE;
            thr_val.gtTh2       = adc_code;
            ctrl                = CSL_VTM_VD_GT_THR2_INTR_EN_SET;
            break;
        case TEST_CSL_VTM_GT_THR1_SET:
            thr_val.thrValidMap = CSL_VTM_GT_TH1_VALID;
            thr_val.gtTh1En     = TRUE;
            thr_val.gtTh1       = adc_code;
            ctrl                = CSL_VTM_VD_GT_THR1_INTR_EN_SET;
            break;
        case TEST_CSL_VTM_LT_THR0_SET:
        default:
            thr_val.thrValidMap = CSL_VTM_LT_TH0_VALID;
            thr_val.ltTh0En     = TRUE;
            thr_val.ltTh0       = adc_code;
            ctrl                = CSL_VTM_VD_LT_THR0_INTR_EN_CLR;
            break;
    }
    #ifdef THR_DEBUG
    printf("CSL_vtmTsSetThresholds : tsid :%d, ltTh0=%d, ltTh0En=%d, gtTh1=%d, gtTh1En=%d, gtTh2=%d, gtTh2En=%d \n",
    ts_id, thr_val.ltTh0, thr_val.ltTh0En, thr_val.gtTh1, thr_val.gtTh1En, thr_val.gtTh2,thr_val.gtTh2En);
    #endif
    /* Set the temperature thresholds */
    CSL_vtmTsSetThresholds (p_cfg,  ts_id, &thr_val, FALSE);
    #ifdef THR_DEBUG
    retVal = CSL_vtmTsGetThresholds(p_cfg, ts_id, &thr_val);
    if (retVal == CSL_PASS)
    {
        printf("CSL_vtmTsGetThresholds : tsid :%d, ltTh0=%d, ltTh0En=%d, gtTh1=%d, gtTh1En=%d, gtTh2=%d, gtTh2En=%d \n",
        ts_id, thr_val.ltTh0, thr_val.ltTh0En, thr_val.gtTh1, thr_val.gtTh1En, thr_val.gtTh2,thr_val.gtTh2En);
    }
    #endif
    /* enable the threshold interrupts */
    CSL_vtmVdThrIntrCtrl(p_cfg, CSL_VTM_VD_DOMAIN_1, ctrl, FALSE);
    /* enable the tracking of temperature events on this VD */
    CSL_vtmVdEvtSelSet (p_cfg, CSL_VTM_VD_DOMAIN_1, vd_temp_evts, FALSE);

}

void test_csl_register_temp_thr_isrs(uintptr_t isr, uintptr_t arg, int32_t thr_code)
{
    printf("In func test_csl_register_temp_thr_isrs!!\n");
    #if 1
    OsalRegisterIntrParams_t intr_params;

    Osal_RegisterInterrupt_initParams(&intr_params);
    printf("After Osal_RegisterInterrupt_initParams...\n");

    switch (thr_code)
    {
        case TEST_CSL_VTM_GT_THR2_SET:
            printf("case 3!!\n");
            intr_params.corepacConfig.isrRoutine = (Osal_IsrRoutine) isr;
            intr_params.corepacConfig.intVecNum  = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0;
            break;
        case TEST_CSL_VTM_GT_THR1_SET:
            printf("case 2!!\n");
            intr_params.corepacConfig.isrRoutine = (Osal_IsrRoutine) isr;
            intr_params.corepacConfig.intVecNum  = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0;
            break;
        case TEST_CSL_VTM_LT_THR0_SET:
        default:
            thr_code = TEST_CSL_VTM_LT_THR0_SET;
            printf("case 1!!\n");
            intr_params.corepacConfig.isrRoutine = (Osal_IsrRoutine) isr;
            intr_params.corepacConfig.intVecNum  = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0;
            break;
    }

    
    #ifdef __TI_ARM_V7R4__
            intr_params.corepacConfig.priority=0x8U;
    #else
    #ifdef __C7100__
            intr_params.corepacConfig.priority=0x01U;
    #else
            intr_params.corepacConfig.priority=0x20U;
    #endif
    #endif
    
    intr_params.corepacConfig.arg = arg;
    Osal_RegisterInterrupt(&intr_params, &gHwiP_handle[thr_code]);
    printf("After Osal_RegisterInterrupt...!!\n");
    #endif

}

void test_csl_unregister_temp_thr_isrs(int32_t thr_code)
{
    int32_t intr_num;
    switch (thr_code)
    {
        case TEST_CSL_VTM_GT_THR1_SET:
            intr_num = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0;
            break;
        case TEST_CSL_VTM_GT_THR2_SET:
            intr_num = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0;
            break;
        case TEST_CSL_VTM_LT_THR0_SET:
        default:
            intr_num = CSLR_MCU_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0;
            thr_code = TEST_CSL_VTM_LT_THR0_SET;
            break;
    }

    Osal_DeleteInterrupt(&gHwiP_handle[thr_code], intr_num);
}

void test_csl_vtm_pvt_sensor_temp_alert (volatile int32_t * temperatureValue)
{
    printf("In function test_csl_vtm_pvt_sensor_temp_alert...\n");
    static int32_t oneTimePrint = 0 ;
    int32_t temp_milli_degrees_read, ts_id;
    //int32_t tmp_value = 0x2342;

    CSL_vtm_adc_code       adc_code;
    CSL_vtm_cfg1Regs       *p_vtm_cfg1_regs;
    CSL_vtm_cfg2Regs       *p_vtm_cfg2_regs;
    CSL_vtm_tsStat_read_ctrl tsStat_read_ctrl = CSL_VTM_TS_READ_DATA_OUT_VAL;
    CSL_vtm_tsStat_val       ts_stat_val;
    CSL_vtm_ts_ctrl_cfg     ts_ctrl_cfg;
    
    int32_t                 high_temp_in_milli_degree_celsius = 123000;
    int32_t                 low_temp_in_milli_degree_celsius  = 105000;
    int32_t                 lt_thr0_val, gt_thr1_val, gt_thr2_val;
    int32_t                 max_temp_read;
    //int32_t                 i; 
    //int32_t                 a = 1234, b =2352, c =232; /* Random val initializations */
    uint32_t               *efuse_base_addr = (uint32_t *)  CSL_VTM_TEST_EFUSE_BASE_ADDR;
    uint8_t                 max_alert,lt_th0_alert,gt_th1_alert,gt_th2_alert;

    p_vtm_cfg1_regs = (CSL_vtm_cfg1Regs *) CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE;
    p_vtm_cfg2_regs = (CSL_vtm_cfg2Regs *) CSL_WKUP_VTM0_MMR_VBUSP_CFG2_BASE;
    #if 1
    lt_thr0_val     = 65000;//TEST_CSL_VTM_LT_THR0_VAL;
    gt_thr1_val     = 70000;//TEST_CSL_VTM_GT_THR1_VAL;
    gt_thr2_val     = 75000;//TEST_CSL_VTM_GT_THR2_VAL;
    #endif

    /* Setup the Efuse values if needed, to simulate an efuse part */
#if defined (CSL_VTM_SS_UNIT) || defined (CSL_VTM_TT_UNIT) || defined (CSL_VTM_FF_UNIT)
    efuse_base_addr[0] = CSL_VTM_VAL_EFUSE_0;
    efuse_base_addr[1] = CSL_VTM_VAL_EFUSE_1;
    efuse_base_addr[2] = CSL_VTM_VAL_EFUSE_2;    
    efuse_base_addr[3] = CSL_VTM_VAL_EFUSE_3;
#endif
    if(0 == oneTimePrint)
    {
        printf("\nVTM threshold test Application version 1.0.0.0 !!\n");

        printf (" efuse 0  is : 0x%x \n \
                efuse 1 is : 0x%x \n \
                efuse 2  is : 0x%x \n \
                efuse 3  is : 0x%x \n", \
                efuse_base_addr[0], \
                efuse_base_addr[1], \
                efuse_base_addr[2], \
                efuse_base_addr[3]);

        extern int32_t gCSL_vtm_pvt_error[4];
        printf ("\nN40 error is : %d \n \
                       P30 error is : %d \n \
                       P125 err  is : %d \n \
                       P150 err  is : %d \n ", \
                       gCSL_vtm_pvt_error[0], \
                       gCSL_vtm_pvt_error[1], \
                       gCSL_vtm_pvt_error[2], \
                       gCSL_vtm_pvt_error[3]); 
        printf ("\n");

        for (ts_id = 0; ts_id < TEST_MAX_SENSOR_FOR_VTM_ALERT; ts_id++)
        {

            ts_ctrl_cfg.valid_map = CSL_VTM_TS_CTRL_MAXT_OUTG_ALERT_VALID   |
                                    CSL_VTM_TS_CTRL_RESET_CTRL_VALID        |
                                    CSL_VTM_TS_CTRL_SOC_VALID               |
                                    CSL_VTM_TS_CTRL_MODE_VALID;

            (void) CSL_vtmTsGetCtrl (p_vtm_cfg2_regs,
                            ts_id,      
                            &ts_ctrl_cfg);
            
            ts_ctrl_cfg.valid_map = CSL_VTM_TS_CTRL_RESET_CTRL_VALID        |
                                    CSL_VTM_TS_CTRL_SOC_VALID               |
                                    CSL_VTM_TS_CTRL_MODE_VALID;

            ts_ctrl_cfg.adc_stat   = CSL_VTM_TS_CTRL_SINGLESHOT_ADC_CONV_IN_PROGRESS;
            ts_ctrl_cfg.mode       = CSL_VTM_TS_CTRL_CONTINUOUS_MODE;
            ts_ctrl_cfg.tsReset    = CSL_VTM_TS_CTRL_SENSOR_NORM_OP;
            (void) CSL_vtmTsSetCtrl (p_vtm_cfg2_regs,
                                    ts_id,      
                                    &ts_ctrl_cfg,
                                    FALSE);

            /* setup the thermal shutdown range */
            (void) CSL_vtmTsSetMaxTOutRgAlertThr( p_vtm_cfg2_regs,
                                                ts_id, 
                                                high_temp_in_milli_degree_celsius,
                                                low_temp_in_milli_degree_celsius);
        }

        printf(" Threshold values programmed in milli degree celsius are \n");
        printf (" \t \
        lt_thr0_val    : %d \
        gt_thr1_val    : %d \
        gt_thr2_val    : %d \n", \
        lt_thr0_val, gt_thr1_val, gt_thr2_val);

        for (ts_id = 0; ts_id < TEST_MAX_SENSOR_FOR_VTM_ALERT; ts_id++)
        {
            CSL_vtmTsConvTempToAdc(lt_thr0_val, ts_id,  &adc_code);
            test_csl_set_temp_thr(adc_code, ts_id, TEST_CSL_VTM_LT_THR0_SET);
            CSL_vtmTsConvTempToAdc(gt_thr1_val, ts_id,  &adc_code);
            test_csl_set_temp_thr(adc_code, ts_id, TEST_CSL_VTM_GT_THR1_SET);
            CSL_vtmTsConvTempToAdc(gt_thr2_val, ts_id,  &adc_code);
            test_csl_set_temp_thr(adc_code, ts_id, TEST_CSL_VTM_GT_THR2_SET);
        }

        oneTimePrint = 1;
    }
    
    
    printf(" Threshold values programmed converted to ADC and threshold set \n");

    #if 1
    /* Register the low, gt_thr1, gt_thr2 Interrupts,
        note same ISR is used for all temperature sensors */
    test_csl_register_temp_thr_isrs((uintptr_t) test_csl_vtm_pvt_sensor_ltThr0_isr, \
                                    (uintptr_t) lt_thr0_val,                        \
                                    TEST_CSL_VTM_LT_THR0_SET);
    test_csl_register_temp_thr_isrs((uintptr_t) test_csl_vtm_pvt_sensor_gtThr1_isr, \
                                    (uintptr_t) gt_thr1_val,                        \
                                    TEST_CSL_VTM_GT_THR1_SET);
    test_csl_register_temp_thr_isrs((uintptr_t) test_csl_vtm_pvt_sensor_gtThr2_isr, \
                                    (uintptr_t) gt_thr2_val,                        \
                                    TEST_CSL_VTM_GT_THR2_SET);
    #endif
    /* print current temperature for all sensors  */
    {
        
        max_temp_read = 0;
        memset(&ts_stat_val,0,sizeof(CSL_vtm_tsStat_val));
        for (ts_id = 0; ts_id < TEST_MAX_SENSOR_FOR_VTM_ALERT; ts_id++)
        {
            CSL_vtmTsGetSensorStat (p_vtm_cfg1_regs, &tsStat_read_ctrl, \
                                    ts_id, &ts_stat_val);
             
             adc_code = ts_stat_val.data_out;
             max_alert = ts_stat_val.maxt_outrg_alert;
             lt_th0_alert = ts_stat_val.lt_th0_alert;
             gt_th1_alert = ts_stat_val.gt_th1_alert;
             gt_th2_alert = ts_stat_val.gt_th2_alert;

             (void) CSL_vtmTsConvADCToTemp (adc_code,
                                        (CSL_vtm_tmpSens_id)     ts_id,
                                         &temp_milli_degrees_read);

            temperatureValue[ts_id] = temp_milli_degrees_read;
             printf (" \
                sensor id                       : %d \
                adc_code                        : %d \
                temp in milli degree celcius    : %d \n", \
                ts_id, adc_code, temp_milli_degrees_read);
             if (max_temp_read < temp_milli_degrees_read)
             {
                 max_temp_read = temp_milli_degrees_read;
             }
        }
        
        
        printf("max_alert : %d, lt_th0_alert : %d, gt_th1_alert : %d, gt_th2_alert : %d\n", max_alert,lt_th0_alert,gt_th1_alert,gt_th2_alert);
        #if 0
        if(0 != max_alert)
        {
            printf("******MAX ALERT******\n");
        }
        if(0 != lt_th0_alert)
        {
            printf ("******LT_TH0_ALERT******\n");
            //printf (" \nSystem at a temperature below the threshold \nSystem running at a safe temperature \n");
        }
        if(0 != gt_th1_alert)
        {
            printf ("******GT_TH1_ALERT******\n");
            //printf (" \nCrossed threshold  System should take action to implement system cooling \n");
        }
        if(0 != gt_th2_alert)
        {
            printf ("******GT_TH2_ALERT******\n");
            //printf (" \nCrossed threshold  System should take critical action to implement system cooling \n");
        }

        printf ("\n");
        #endif

        #if 0
        if (gAuto_test == TRUE)
        {
            /* Set the LT_THR0, GT_THR1, GT_THR2 values */
            lt_thr0_val = max_temp_read + 500;
            gt_thr1_val = lt_thr0_val + 1800;
            gt_thr2_val = gt_thr1_val + 1800;
        }
        #endif
          
        #if 0
        i = 0;
        while (TRUE)
        {
            int32_t        temp[CSL_VTM_TEST_NUM_SENSORS];
            /* if gt_thr2 is fired, wait for the cooling to take place */
            while ((g_gt_thr2_alert_fired == TRUE) && \
                   (g_lt_thr0_alert_fired == FALSE))
            {
                printf(" In NOP loop \n");
                /* No operations until cooling takes place */
                asm (" nop ");
            }
            /* have some computations to raise the temperature */
            /* Do not do any computations if temperature is above normal */
            tmp_value += a*b;
            tmp_value += b/c;
            a = b;
            b = c;
            c= tmp_value;

            for (ts_id = 0; ts_id < CSL_VTM_TEST_NUM_SENSORS; ts_id++)
            {
                CSL_vtmTsGetSensorStat (p_vtm_cfg1_regs, &tsStat_read_ctrl, \
                                        ts_id, &ts_stat_val);
                 
                adc_code = ts_stat_val.data_out;
                (void) CSL_vtmTsConvADCToTemp (adc_code,
                                               (CSL_vtm_tmpSens_id) ts_id,
                                               &temp[ts_id]);
            }
            printf(" Getting current temp... \n");
            if (i == 8096)
            {
                 i = 0;
                 printf ("s0_temp: %d  s1_temp: %d s2_temp: %d  s3_temp: %d  s4_temp: %d \r", temp[0], temp[1], temp[2], temp[3], temp[4]);
            }

            i++;
            /* Check if all alerts are fired, exit if done */
            g_all_thr_alerts_fired = g_lt_thr0_alert_fired & \
                                     g_gt_thr1_alert_fired & \
                                     g_gt_thr2_alert_fired;

            if ((g_all_thr_alerts_fired == TRUE) && 
                (gAuto_test == TRUE))
            {
                printf(" break statment... \n");
                break;
            }
        }
        #endif
    }

    printf("\nApplication is completed!!\n");
#if defined (UNITY_INCLUDE_CONFIG_H)
    UART_printf("\n All tests have passed. \n");
    TEST_PASS();
#endif

}

#if 0
void test_csl_vtm_pvt_sensor_temp_alert_runner(void)
{
    /* @description:Test runner for VTM tests

       @requirements: PRSDK-6371, PRSDK-7237, PRSDK-7696, PRSDK-8209, PRSDK-7407

       @cores: mcu1_0 */
#if defined(UNITY_INCLUDE_CONFIG_H)
    UNITY_BEGIN();
    RUN_TEST (test_csl_vtm_pvt_sensor_temp_alert);
    UNITY_END();
    /* Function to print results defined in our unity_config.h file */
    print_unityOutputBuffer_usingUARTstdio();
#else
    test_csl_vtm_pvt_sensor_temp_alert();
#endif
    return;
}

int32_t main(void)
{
    
    Board_initCfg boardCfg;
    Board_STATUS  boardStatus;
    
    boardCfg = BOARD_INIT_UNLOCK_MMR | 
        BOARD_INIT_MODULE_CLOCK | 
        BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_UART_STDIO;
    
    boardStatus = Board_init(boardCfg);
    if (boardStatus != BOARD_SOK)
    {
        #if defined (UNITY_INCLUDE_CONFIG_H)
            TEST_FAIL();
        #endif
    }
    else
    {
       (void) test_csl_vtm_pvt_sensor_temp_alert_runner();
        while (1)
        {
        }
    }
}

#endif

2. The temperature sensor is programmed for continuous mode. EFUSE value are not set by us. That can be seen in the logs. Please find attached the logs :

(i) Log when ISR registration is enabled ((Application hangs at run time) :

Fullscreen Stress_test_with_isr_reg.log Download

=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2020.12.05 21:47:58 =~=~=~=~=~=~=~=~=~=~=~=

U-Boot SPL 2019.01-00005-g29c2781fee (Jan 21 2020 - 18:50:05 +0900)
SYSFW ABI: 2.9 (firmware rev 0x0013 '19.12.1-v2019.12a (Terrific Lla')
Reading on-board EEPROM at 0x50 failed 1
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41ca13dc register: 0x23!
Trying to boot from MMC2
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41ca13dc register: 0x23!
Loading Environment from MMC... *** Warning - No MMC card found, using default environment

** File not found /lib/firmware/j7-main-r5f0_0-fw **
** File not found /lib/firmware/j7-mcu-r5f0_0-fw **
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.1(release):ti2019.04-rc1
NOTICE:  BL31: Built : 12:46:22, Nov 18 2019
I/TC: 
I/TC: OP-TEE version: ti2019.02 #1 2019. 11. 18. (월) 03:45:57 UTC aarch64
I/TC: Initialized

U-Boot SPL 2019.01-00005-gb84b6473df-dirty (Jan 21 2020 - 19:58:46 +0900)
Reading on-board EEPROM at 0x50 failed 1
Trying to boot from MMC2


U-Boot 2019.01-00005-gb84b6473df-dirty (Jan 21 2020 - 20:20:15 +0900)

Model: Texas Instruments K3 J721E SoC
DRAM:  4 GiB
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment

In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Reading on-board EEPROM at 0x50 failed 1
Net:   Could not get PHY for ethernet@046000000: addr 0
phy_connect() failed
eth-1: ethernet@046000000
Hit any key to stop autoboot:  2  1  0 
** Unable to read file /lib/firmware/j7-main-r5f0_0-fw **
** Unable to read file /lib/firmware/j7-main-r5f0_1-fw **
** Unable to read file /lib/firmware/j7-main-r5f1_0-fw **
** Unable to read file /lib/firmware/j7-c66_0-fw **
** Unable to read file /lib/firmware/j7-c66_1-fw **
** Unable to read file /lib/firmware/j7-c71_0-fw **
19856400 bytes read in 825 ms (23 MiB/s)
## Starting application at 0x80080000 ...
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Filesystem already exist!!
Starting MMC/SD memory card driver... SD
ethernet driver start
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
main: this fixed by sungwpark at last
setting env variables.
# 

# 

# 

# flashctl -p /dev/fs0 -e

# dd if=/sd/sbl/sbl_cust_img_mcu1_0_release.tiimage of=/dev/fs0p0 bs=32k

6+1 records in
6+1 records out
# dd if=/sd/sbl/sysfw.bin of=/dev/fs0p0 bs=32k seek=1 obs=512k

8+1 records in
0+1 records out
# dd if=/sd/sbl/can_boot_app_mcu_rtos_mcu1_0_release_ospi.appimage of=/dev/fs0p0 bs=32k seek=1 obs=1024k

6+1 records in
0+1 records out
# dd if=/sd/sbl/atf_optee.appimage of=/dev/fs0p0 bs=32k seek=1 obs=1536k

12+1 records in
0+1 records out
# dd if=/sd/sbl/ifs_qnx_vpu1_vp.appimage of=/dev/fs0p0 bs=32k seek=1 obs=4096k

707+1 records in
5+1 records out
# dd if=/sd/sbl/lateapp1 of=/dev/fs0p0 bs=32k seek=1 obs=39936k

148+1 records in
0+1 records out
# dd if=/sd/sbl/lateapp2 of=/dev/fs0p0 bs=32k seek=1 obs=47104k

187+1 records in
0+1 records out
# 

# 

# NOTICE:  BL31: v2.2(release):ti2020.00
NOTICE:  BL31: Built : 22:09:07, Dec  4 2020
I/TC: 
I/TC: OP-TEE version: ti2020.00 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Fri Dec  4 16:39:23 UTC 2020 aarch64
I/TC: Initialized
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Starting MMC/SD memory card driver... SD
j7ospi_phy_config: tx/rd delay = 1f
Mailbox_plugInterrupt: interrupt Number 507, arg 0x1011EB78
j7ospi_phy_config: tethernet driver start
x/rd delay = 87
Mailbox_plugInterrupt: interrupt Number 508, arg 0x1011ED10
Mailbox_plugInterrupt: interrupt Number 509, arg 0x1011EEA8
Mailbox_plugInterrupt: interrupt Number 510, arg 0x1011F040
Mailbox_plugInterrupt: interrupt Number 511, arg 0x1011F1D8
Starting TI IPC Resmgr
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
on: No such file or directory (./fs/SwUpdate)
Unable to access "/dev/fs0p1" (2)
filesystem create done
sh: /fs/startup.sh: No such file or directory
setting env variables.
# j7ospi_phy_config: tx/rd delay = 1f
j7ospi_phy_config: tx/rd delay = 87


# 

# 

# 

# mount -tdos -oexe=all /dev/sd0t12 /sd

# cp -r /sd/sbl/fs ./

# shutdown

Killed 
NOTICE:  BL31: v2.2(release):ti2020.00
NOTICE:  BL31: Built : 22:09:07, Dec  4 2020
I/TC: 
I/TC: OP-TEE version: ti2020.00 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Fri Dec  4 16:39:23 UTC 2020 aarch64
I/TC: Initialized
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Starting MMC/SD memory card driver... SD
j7ospi_phy_config: tx/rd delay = 1f
j7ospi_phy_config: ethernet driver start
tx/rdMailbox_plugInterrupt: interrupt Number 507, arg 0x1011EB78
 delay = 87
Mailbox_plugInterrupt: interrupt Number 508, arg 0x1011ED10
Mailbox_plugInterrupt: interrupt Number 509, arg 0x1011EEA8
Mailbox_plugInterrupt: interrupt Number 510, arg 0x1011F040
Mailbox_plugInterrupt: interrupt Number 511, arg 0x1011F1D8
Starting TI IPC Resmgr
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
src/MCU/McuUpdateHandler.c:messageReceiver:467(): INFO: Wait for MCU connection.
Filesystem already exist!!
/fs/startup.sh[2]: 
: cannot execute - No such file or directory
startup.sh start!!

/fs/startup.sh[4]: 
: cannot execute - No such file or directory
Malformed integer '4
'
mount: Can't mount /sd
 (type dos) 
mount: Possible reason: No such file or directory 
/fs/startup.sh[7]: 
: cannot execute - No such file or directory
/fs/startup.sh[8]: cd: /fs/bin
 - No such file or directory
/fs/startup.sh[9]: ./shmemallocator
: cannot execute - No such file or directory
/fs/startup.sh[10]: 
: cannot execute - No such file or directory
/fs/startup.sh[11]: cd: /fs/ph00
 - No such file or directory
/fs/startup.sh[12]: ./LogFlushDaemon
: cannot execute - No such file or directory
/fs/startup.sh[13]: ./TimebaseEngine
: cannot execute - No such file or directory
setting env variables.
# 

# 

# 

# 

# cd fs/bin

# ./shmemallocator

# ./vx_app_qnx_arm_remote_log.out &

[1] 245779
[MCU2_0]     35.197732 s: CIO: Init ... Done !!!

[MCU2_0]     35.197801 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU2_0]     35.197841 s: APP: Init ... !!!

[MCU2_0]     35.197859 s: SCICLIENT: Init ... !!!

[MCU2_0]     35.197944 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU2_0]     35.197982 s: SCICLIENT: DMSC FW revision 0x14  

[MCU2_0]     35.198006 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU2_0]     35.198030 s: SCICLIENT: Init ... Done !!!

[MCU2_0]     35.198050 s: UDMA: Init ... !!!

[MCU2_0]     35.198984 s: UDMA: Init ... Done !!!

[MCU2_0]     35.199040 s: MEM: Init ... !!!

[MCU2_0]     35.199077 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2800000 of size 16777216 bytes !!!

[MCU2_0]     35.199135 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 67108864 bytes !!!

[MCU2_0]     35.199181 s: MEM: Init ... Done !!!

[MCU2_0]     35.199200 s: FVID2: Init ... !!!

[MCU2_0]     35.199249 s: FVID2: Init ... Done !!!

[MCU2_0]     35.199272 s: VHWA: Init ... !!!

[MCU2_0]     35.199290 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2

[MCU2_0]     35.199435 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.199464 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2

[MCU2_0]     35.199606 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.199631 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2

[MCU2_0]     35.199744 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.199768 s: VHWA: DOF Init ... !!!

[MCU2_0]     35.203526 s: VHWA: DOF Init ... Done !!!

[MCU2_0]     35.203577 s: VHWA: LDC Init ... !!!

[MCU2_0]     35.205599 s: VHWA: LDC Init ... Done !!!

[MCU2_0]     35.205651 s: VHWA: MSC Init ... !!!

[MCU2_0]     35.211852 s: VHWA: MSC Init ... Done !!!

[MCU2_0]     35.211904 s: VHWA: NF Init ... !!!

[MCU2_0]     35.213006 s: VHWA: NF Init ... Done !!!

[MCU2_0]     35.213052 s: VHWA: SDE Init ... !!!

[MCU2_0]     35.214633 s: VHWA: SDE Init ... Done !!!

[MCU2_0]     35.214685 s: VHWA: VISS Init ... !!!

[MCU2_0]     35.219771 s: VHWA: VISS Init ... Done !!!

[MCU2_0]     35.219852 s: VHWA: VDEC Init ... !!!

[MCU2_0]     35.258157 s: VHWA: VDEC Init ... Done !!!

[MCU2_0]     35.258357 s: VHWA: VENC Init ... !!!

[MCU2_0]     35.307302 s: VHWA: VENC Init ... Done !!!

[MCU2_0]     35.307356 s: VHWA: Init ... Done !!!

[MCU2_0]     35.307382 s: IPC: Init ... !!!

[MCU2_0]     35.307414 s: IPC: 7 CPUs participating in IPC !!!

[MCU2_0]     35.314214 s: IPC: Init ... Done !!!

[MCU2_0]     35.314276 s: APP: Syncing with 6 CPUs ... !!!

[MCU2_0]     35.314314 s: APP: Syncing with 6 CPUs ... Done !!!

[MCU2_0]     35.314343 s: REMOTE_SERVICE: Init ... !!!

[MCU2_0]     35.315917 s: REMOTE_SERVICE: Init ... Done !!!

[MCU2_0]     35.315979 s: ETHFW: Init ... !!!

[MCU2_0]     35.387703 s: ETHFW: Version   : 0.01.01

[MCU2_0]     35.387763 s: ETHFW: Build Date: Dec  4, 2020

[MCU2_0]     35.387789 s: ETHFW: Build Time: 21:10:49

[MCU2_0]     35.387828 s: ETHFW: Commit SHA: 

[MCU2_0]     35.387856 s: ETHFW: Init ... DONE !!!

[MCU2_0]     35.387882 s: ETHFW: Remove server Init ... !!!

[MCU2_0]     35.431826 s: ETHFW: Remove server Init ... DONE !!!

[MCU2_0]     35.431954 s: APP: Setup Dual Vout !!!

[MCU2_0]     35.444950 s: APP: Setup Dual Vout (0)... !!!

[MCU2_0]     35.445054 s:  VX_ZONE_INIT:Enabled

[MCU2_0]     35.445088 s:  VX_ZONE_ERROR:Enabled

[MCU2_0]     35.445111 s:  VX_ZONE_WARNING:Enabled

[MCU2_0]     35.448660 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!

[MCU2_0]     35.448704 s: APP: OpenVX Target kernel init ... !!!

[MCU2_0]     35.455543 s: APP: OpenVX Target kernel init ... Done !!!

[MCU2_0]     35.455593 s: CSI2RX: Init ... !!!

[MCU2_0]     35.455613 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2

[MCU2_0]     35.455701 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.455731 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2

[MCU2_0]     35.455902 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.455935 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2

[MCU2_0]     35.456077 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.456104 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2

[MCU2_0]     35.456193 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.456219 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2

[MCU2_0]     35.456306 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.457015 s: CSI2RX: Init ... Done !!!

[MCU2_0]     35.457060 s: CSI2TX: Init ... !!!

[MCU2_0]     35.457084 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2

[MCU2_0]     35.457168 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.457196 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2

[MCU2_0]     35.457337 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.457361 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2

[MCU2_0]     35.457471 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     35.458081 s: CSI2TX: Init ... Done !!!

[MCU2_0]     35.458129 s: ISS: Init ... !!!

[MCU2_0]     35.458187 s: Found sensor IMX390-UB953_D3 at location 0 

[MCU2_0]     35.458236 s: Found sensor AR0233-UB953_MARS at location 1 

[MCU2_0]     35.458276 s: Found sensor AR0820-UB953_LI at location 2 

[MCU2_0]     35.458316 s: Found sensor UB9702_TESTPATTERN at location 3 

[MCU2_0]     35.458353 s: Found sensor MOBIS-ISP at location 4 

[MCU2_0]     35.458389 s: Found sensor MOBIS-SVM-ISPLESS at location 5 

[MCU2_0]     35.458427 s: Found sensor MOBIS-RS-ISPLESS at location 6 

[MCU2_0]     35.458452 s: IssSensor_Init ... Done !!!

[MCU2_0]     35.458527 s: vissRemoteServer_Init ... Done !!!

[MCU2_0]     35.458582 s: IttRemoteServer_Init ... Done !!!

[MCU2_0]     35.458610 s: UDMA Copy: Init ... !!!

[MCU2_0]     35.459758 s: UDMA Copy: Init ... Done !!!

[MCU2_0]     35.459830 s: APP: Init ... Done !!!

[MCU2_0]     35.459858 s: APP: Run ... !!!

[MCU2_0]     35.459877 s: IPC: Starting echo test ...

[MCU2_0]     35.462444 s: APP: Run ... Done !!!

[MCU2_0]     35.464401 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[P] C7X_1[.] 

[MCU2_0]     35.464637 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] 

[MCU2_0]     35.464767 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] 

[MCU2_0]     35.464936 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 

[MCU2_0]     35.465048 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 

[MCU3_0]     35.221004 s: CIO: Init ... Done !!!

[MCU3_0]     35.221091 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU3_0]     35.221135 s: APP: Init ... !!!

[MCU3_0]     35.221155 s: SCICLIENT: Init ... !!!

[MCU3_0]     35.221247 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU3_0]     35.221284 s: SCICLIENT: DMSC FW revision 0x14  

[MCU3_0]     35.221307 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU3_0]     35.221330 s: SCICLIENT: Init ... Done !!!

[MCU3_0]     35.221352 s: MEM: Init ... !!!

[MCU3_0]     35.221384 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!!

[MCU3_0]     35.221437 s: MEM: Init ... Done !!!

[MCU3_0]     35.221459 s: IPC: Init ... !!!

[MCU3_0]     35.221490 s: IPC: 7 CPUs participating in IPC !!!

[MCU3_0]     35.241281 s: IPC: Init ... Done !!!

[MCU3_0]     35.241524 s: APP: Syncing with 6 CPUs ... !!!

[MCU3_0]     35.314315 s: APP: Syncing with 6 CPUs ... Done !!!

[MCU3_0]     35.314358 s: REMOTE_SERVICE: Init ... !!!

[MCU3_0]     35.315866 s: REMOTE_SERVICE: Init ... Done !!!

[MCU3_0]     35.315922 s: APP: Init ... Done !!!

[MCU3_0]     35.315948 s: APP: Run ... !!!

[MCU3_0]     35.315966 s: IPC: Starting echo test ...

[MCU ... Done !!!

[MCU3_0]     35.319658 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[.] 

[MCU3_0]     35.319762 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P] 

[MCU3_0]     35.320350 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[P] 

[MCU3_0]     35.320599 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 

[MCU3_0]     35.464212 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 

[MCU3_1]     35.222166 s: CIO: Init ... Done !!!

[MCU3_1]     35.222249 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU3_1]     35.222294 s: APP: Init ... !!!

[MCU3_1]     35.222315 s: SCICLIENT: Init ... !!!

[MCU3_1]     35.222405 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU3_1]     35.222443 s: SCICLIENT: DMSC FW revision 0x14  

[MCU3_1]     35.222467 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU3_1]     35.222491 s: SCICLIENT: Init ... Done !!!

[MCU3_1]     35.222512 s: MEM: Init ... !!!

[MCU3_1]     35.222544 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!!

[MCU3_1]     35.222596 s: MEM: Init ... Done !!!

[MCU3_1]     35.222617 s: IPC: Init ... !!!

[MCU3_1]     35.222648 s: IPC: 7 CPUs participating in IPC !!!

[MCU3_1]     35.244631 s: IPC: Init ... Done !!!

[MCU3_1]     35.244871 s: APP: Syncing with 6 CPUs ... !!!

[MCU3_1]     35.314316 s: APP: Syncing with 6 CPUs ... Done !!!

[MCU3_1]     35.314356 s: REMOTE_SERVICE: Init ... !!!

[MCU3_1]     35.315846 s: REMOTE_SERVICE: Init ... Done !!!

[MCU3_1]     35.315907 s: APP: Init ... Done !!!

[MCU3_1]     35.315933 s: APP: Run ... !!!

[MCU3_1]     35.315952 s: IPC: Starting echo test ...

[MCU3_1]     35.318629 s: APP: Run ... Done !!!

[MCU3_1]     35.319577 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] 

[MCU3_1]     35.319720 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] 

[MCU3_1]     35.320309 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] 

[MCU3_1]     35.320516 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 

[MCU3_1]     35.464225 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 

[C6x_1 ]     35.260358 s: CIO: Init ... Done !!!

[C6x_1 ]     35.260400 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>

[C6x_1 ]     35.260418 s: APP: Init ... !!!

[C6x_1 ]     35.260429 s: SCICLIENT: Init ... !!!

[C6x_1 ]     35.260532 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C6x_1 ]     35.260551 s: SCICLIENT: DMSC FW revision 0x14  

[C6x_1 ]     35.260563 s: SCICLIENT: DMSC FW ABI revision 3.0

[C6x_1 ]     35.260578 s: SCICLIENT: Init ... Done !!!

[C6x_1 ]     35.260589 s: UDMA: Init ... !!!

[C6x_1 ]     35.261794 s: UDMA: Init ... Done !!!

[C6x_1 ]     35.261820 s: MEM: Init ... !!!

[C6x_1 ]     35.261832 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!

[C6x_1 ]     35.261849 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_1 ]     35.261864 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!

[C6x_1 ]     35.261881 s: MEM: Init ... Done !!!

[C6x_1 ]     35.261889 s: IPC: Init ... !!!

[C6x_1 ]     35.261903 s: IPC: 7 CPUs participating in IPC !!!

[C6x_1 ]     35.268386 s: IPC: Init ... Done !!!

[C6x_1 ]     35.268426 s: APP: Syncing with 6 CPUs ... !!!

[C6x_1 ]     35.314313 s: APP: Syncing with 6 CPUs ... Done !!!

[C6x_1 ]     35.314324 s: REMOTE_SERVICE: Init ... !!!

[C6x_1 ]     35.314997 s: REMOTE_SERVICE: Init ... Done !!!

[C6x_1 ]     35.315040 s:  VX_ZONE_INIT:Enabled

[C6x_1 ]     35.315050 s:  VX_ZONE_ERROR:Enabled

[C6x_1 ]     35.315059 s:  VX_ZONE_WARNING:Enabled

[C6x_1 ]     35.315899 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!

[C6x_1 ]     35.315916 s: APP: OpenVX Target kernel init ... !!!

[C6x_1 ]     35.316204 s: APP: OpenVX Target kernel init ... Done !!!

[C6x_1 ]     35.316225 s: UDMA Copy: Init ... !!!

[C6x_1 ]     35.317867 s: UDMA Copy: Init ... Done !!!

[C6x_1 ]     35.317887 s: APP: Init ... Done !!!

[C6x_1 ]     35.318250 s: APP: Run ... !!!

[C6x_1 ]     35.318262 s: IPC: Starting echo test ...

[C6x_1 ]     35.319712 s: APP: Run ... Done !!!

[C6x_1 ]     35.320161 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] 

[C6x_1 ]     35.320256 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] 

[C6x_1 ]     35.320307 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[.] C7X_1[P] 

[C6x_1 ]     35.320362 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 

[C6x_1 ]     35.464143 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 

[C6x_2 ]     35.261146 s: CIO: Init ... Done !!!

[C6x_2 ]     35.261179 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>

[C6x_2 ]     35.261193 s: APP: Init ... !!!

[C6x_2 ]     35.261200 s: SCICLIENT: Init ... !!!

[C6x_2 ]     35.261321 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C6x_2 ]     35.261334 s: SCICLIENT: DMSC FW revision 0x14  

[C6x_2 ]     35.261343 s: SCICLIENT: DMSC FW ABI revision 3.0

[C6x_2 ]     35.261353 s: SCICLIENT: Init ... Done !!!

[C6x_2 ]     35.261372 s: UDMA: Init ... !!!

[C6x_2 ]     35.262398 s: UDMA: Init ... Done !!!

[C6x_2 ]     35.262424 s: MEM: Init ... !!!

[C6x_2 ]     35.262437 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!

[C6x_2 ]     35.262454 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_2 ]     35.262469 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!

[C6x_2 ]     35.262485 s: MEM: Init ... Done !!!

[C6x_2 ]     35.262493 s: IPC: Init ... !!!

[C6x_2 ]     35.262506 s: IPC: 7 CPUs participating in IPC !!!

[C6x_2 ]     35.269302 s: IPC: Init ... Done !!!

[C6x_2 ]     35.269332 s: APP: Syncing with 6 CPUs ... !!!

[C6x_2 ]     35.314313 s: APP: Syncing with 6 CPUs ... Done !!!

[C6x_2 ]     35.314324 s: REMOTE_SERVICE: Init ... !!!

[C6x_2 ]     35.314994 s: REMOTE_SERVICE: Init ... Done !!!

[C6x_2 ]     35.315036 s:  VX_ZONE_INIT:Enabled

[C6x_2 ]     35.315046 s:  VX_ZONE_ERROR:Enabled

[C6x_2 ]     35.315055 s:  VX_ZONE_WARNING:Enabled

[C6x_2 ]     35.315886 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!

[C6x_2 ]     35.315902 s: APP: OpenVX Target kernel init ... !!!

[C6x_2 ]     35.316202 s: APP: OpenVX Target kernel init ... Done !!!

[C6x_2 ]     35.316225 s: UDMA Copy: Init ... !!!

[C6x_2 ]     35.317988 s: UDMA Copy: Init ... Done !!!

[C6x_2 ]     35.318009 s: APP: Init ... Done !!!

[C6x_2 ]     35.318389 s: APP: Run ... !!!

[C6x_2 ]     35.318399 s: IPC: Starting echo test ...

[C6x_2 ]     35.319939 s: APP: Run ... Done !!!

[C6x_2 ]     35.320368 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[s] C7X_1[P] 

[C6x_2 ]     35.320404 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 

[C6x_2 ]     35.320487 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] 

[C6x_2 ]     35.320518 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 

[C6x_2 ]     35.464167 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 

[C7x_1 ]     35.267984 s: CIO: Init ... Done !!!

[C7x_1 ]     35.268009 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[C7x_1 ]     35.268028 s: APP: Init ... !!!

[C7x_1 ]     35.268037 s: SCICLIENT: Init ... !!!

[C7x_1 ]     35.268098 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C7x_1 ]     35.268113 s: SCICLIENT: DMSC FW revision 0x14  

[C7x_1 ]     35.268125 s: SCICLIENT: DMSC FW ABI revision 3.0

[C7x_1 ]     35.268138 s: SCICLIENT: Init ... Done !!!

[C7x_1 ]     35.268147 s: UDMA: Init ... !!!

[C7x_1 ]     35.268300 s: UDMA: Init ... Done !!!

[C7x_1 ]     35.268312 s: MEM: Init ... !!!

[C7x_1 ]     35.268325 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!

[C7x_1 ]     35.268347 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!

[C7x_1 ]     35.268367 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!

[C7x_1 ]     35.268384 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!

[C7x_1 ]     35.268402 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 251658240 bytes !!!

[C7x_1 ]     35.268421 s: MEM: Init ... Done !!!

[C7x_1 ]     35.268429 s: IPC: Init ... !!!

[C7x_1 ]     35.268440 s: IPC: 7 CPUs participating in IPC !!!

[C7x_1 ]     35.270895 s: IPC: Init ... Done !!!

[C7x_1 ]     35.270910 s: APP: Syncing with 6 CPUs ... !!!

[C7x_1 ]     35.314315 s: APP: Syncing with 6 CPUs ... Done !!!

[C7x_1 ]     35.314328 s: REMOTE_SERVICE: Init ... !!!

[C7x_1 ]     35.314594 s: REMOTE_SERVICE: Init ... Done !!!

[C7x_1 ]     35.314655 s:  VX_ZONE_INIT:Enabled

[C7x_1 ]     35.314668 s:  VX_ZONE_ERROR:Enabled

[C7x_1 ]     35.314679 s:  VX_ZONE_WARNING:Enabled

[C7x_1 ]     35.314977 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!

[C7x_1 ]     35.314991 s: APP: OpenVX Target kernel init ... !!!

[C7x_1 ]     35.315103 s: APP: OpenVX Target kernel init ... Done !!!

[C7x_1 ]     35.315123 s: APP: Init ... Done !!!

[C7x_1 ]     35.315134 s: APP: Run ... !!!

[C7x_1 ]     35.315142 s: IPC: Starting echo test ...

[C7x_1 ]     35.315717 s: APP: Run ... Done !!!

[C7x_1 ]     35.319452 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[.] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] 

[C7x_1 ]     35.319655 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] 

[C7x_1 ]     35.320180 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[s] 

[C7x_1 ]     35.320355 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 

[C7x_1 ]     35.464232 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 

# 

# 

# 

# 

# ./vx    ./vx_app_s          ./vx_app_stress_test.out --cfg ap  app_stress_1            app_stress_100.cfg 

APP: Init QNX ... !!!
appIpcInit: IPC: Init QNX ... !!!
appIpcInit: IPC: Init ... Done !!!
    63.484634 s: REMOTE_SERVICE: Init ... !!!
    63.484784 s: REMOTE_SERVICE: Init ... Done !!!
APP: Init ... Done !!!
    63.484827 s:  VX_ZONE_INIT:Enabled
    63.484842 s:  VX_ZONE_ERROR:Enabled
    63.484857 s:  VX_ZONE_WARNING:Enabled
    63.485092 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    63.485130 s:  VX_ZONE_INIT:[tivxHostInit:48] Initialization Done for HOST !!!
In app_set_cfg_default...
sleepInUsec : 100 
IP address : 10.32.32.40 
In app_init...

Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_0: TOTAL LOAD =   1.89 % ( HWI =   0.35 %, SWI =   0. 6 % )
CPU: mcu3_0: TOTAL LOAD =   0.44 % ( HWI =   0. 6 %, SWI =   0. 2 % )
CPU: mcu3_1: TOTAL LOAD =   0.44 % ( HWI =   0. 6 %, SWI =   0. 2 % )
CPU: C66X_1: TOTAL LOAD =   1.47 % ( HWI =   0. 2 %, SWI =   0. 2 % )
CPU: C66X_2: TOTAL LOAD =   1.34 % ( HWI =   0. 2 %, SWI =   0. 2 % )
CPU:  C7X_1: TOTAL LOAD =   0.69 % ( HWI =   0. 9 %, SWI =   0. 5 % )

[MCU2_0]     64.001367 s: In function test_csl_vtm_pvt_sensor_temp_alert...

[MCU2_0]     64.001433 s: 

[MCU2_0]     64.001462 s: VTM threshold test Application version 1.0.0.0 !!

[MCU2_0]     64.001524 s:  efuse 0  is : 0x0 

[MCU2_0]     64.001557 s:                  efuse 1 is : 0x0 

[MCU2_0]     64.001591 s:                  efuse 2  is : 0x0 

[MCU2_0]     64.001621 s:                  efuse 3  is : 0x0 

[MCU2_0]     64.001645 s: 

[MCU2_0]     64.001663 s: N40 error is : 0 

[MCU2_0]     64.001689 s:                         P30 error is : 0 

[MCU2_0]     64.001721 s:                         P125 err  is : 0 

[MCU2_0]     64.001753 s:                         P150 err  is : 0 

[MCU2_0]     64.001777 s:  

[MCU2_0]     64.002326 s:  Threshold values programmed in milli degree celsius are 

[MCU2_0]     64.002394 s:  	         lt_thr0_val    : 65000         gt_thr1_val    : 70000         gt_thr2_val    : 75000 

[MCU2_0]     64.002594 s:  Threshold values programmed converted to ADC and threshold set 

[MCU2_0]     64.002648 s: In func test_csl_register_temp_thr_isrs!!

[MCU2_0]     64.002686 s: After Osal_RegisterInterrupt_initParams...

[MCU2_0]     64.002713 s: case 1!!

[MCU2_0]     64.002791 s: After Osal_RegisterInterrupt...!!

[MCU2_0]     64.002867 s: In func test_csl_register_temp_thr_isrs!!

[MCU2_0]     64.002907 s: After Osal_RegisterInterrupt_initParams...

[MCU2_0]     64.002934 s: case 2!!

[MCU2_0]     64.002986 s: After Osal_RegisterInterrupt...!!

[MCU2_0]     64.003022 s: In func test_csl_register_temp_thr_isrs!!

[MCU2_0]     64.003057 s: After Osal_RegisterInterrupt_initParams...

[MCU2_0]     64.003082 s: case 3!!


# 
# 
# 
# 
#

(ii) Log when ISR registration is disabled (Application has no run time error, the temperature readings are correct, but no alerts) : Stress_test_without_isr_reg.log

3. As you suggested I used the CSL_vtmTsGetThresholds() API to read the current threshold and enabled/disabled status for a given temperature sensor ID. Also the temperature rise can be seen in the sensor reading. The values are reflecting correctly.

4. We tried to find exact location where the application hangs, using a debugger. After the function call test_csl_register_temp_thr_isrs( line 461) , when registering threshold TEST_CSL_VTM_GT_THR2_SET (line 280) the application hangs and the debugger shows the following error messages :

[MAIN_Cortex_R5_0_0] 00256.528 TaskGetEnv: FATAL: NDK not initialized
00256.528 fdOpenSession: OOM
00256.528 TaskGetEnv: FATAL: NDK not initialized
00256.528 fdOpenSession: OOM
[UDMA] [Error] Sciclient event config failed!!!
[UDMA] [Error] Event config failed!!
[UDMA] [Error] Global master event register failed!!!
[Error] UDMA init failed!!
[NIMU_NDK] Registration of the CPSW Successful
ti.sysbios.gates.GateMutex: line 99: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details.
xdc.runtime.Error.raise: terminating execution

Please go through the logs and let us know your observations.

Thanks,

Dipti

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Hi Dipti,

Thanks for all the details. I will check internally with the RTOS expert and get back in couple of days.

Best Regards,
Keerthy

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Dipti,

Apologies for the long silence on this. Couple of more questions:

1) On your setup have you verified that the thermal alert baremetal application works as expected and fires interrupts?
2) Does your hardware have Efuse values blown and they are not 0s?

I will start trying baremetal application at my end today.

Best Regards,
Keerthy

0 Keerthy J over 4 years ago in reply to Keerthy J

TI__Guru**** 164680 points

Dipti,

I used csl_vtm_pvt_sensor_temp_alert_mcu1_0_release.xer5f on RTOS SDK 7.0 and i see that thresholds are getting hit & nicely prints are
coming up from the CSL xer5f.

P30 error is : 0
                        P125 err is : 0
                        P150 err is : 0

                 sensor id                       : 0                 adc_code                        : 415                 temp in milli degree celcius    : 68291
                 sensor id                       : 1                 adc_code                        : 420                 temp in milli degree celcius    : 69371
                 sensor id                       : 2                 adc_code                        : 418                 temp in milli degree celcius    : 68939
                 sensor id                       : 3                 adc_code                        : 420                 temp in milli degree celcius    : 69371
                 sensor id                       : 4                 adc_code                        : 416                 temp in milli degree celcius    : 68507

Threshold values programmed in milli degree celsius are
                    lt_thr0_val    : 69871            gt_thr1_val    : 71671            gt_thr2_val    : 73471
0_temp: 69371 s1_temp: 69586 s2_temp: 69801 s3_temp: 70230 s4_temp: 69371

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 69871
System running at a safe temperature
0_temp: 69155 s1_temp: 70016 s2_temp: 70016 s3_temp: 70016 s4_temp: 69586

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 69871
System running at a safe temperature

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 69871
System running at a safe temperature
0_temp: 70230 s1_temp: 70230 s2_temp: 70016 s3_temp: 71086 s4_temp: 69586

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 69871
System running at a safe temperature

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 69871
System running at a safe temperature

got gtThr1 interrupt

Crossed threshold 71671 System should take action to implement system cooling

It goes on.

So can you please confirm that on your setup you are able to get these interrupts with the baremetal csl application?

Best Regards,
Keerthy

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Dipti Natu said:
[MAIN_Cortex_R5_0_0] 00256.528 TaskGetEnv: FATAL: NDK not initialized

Dipti,

It took sometime while i was debugging with our expert. The root cause is that the CSL library for temperature alerts
was entirely written for MCU R5F0 & you are using MAIN_R5F0.

That means all your interrupt numbers are wrong.

You have used 158, 157, 156 but Main R5F interrupt numbers are 327, 328, 329.

So i first request you to try on MCU R5F0 to check if everything works as expected & only if that cannot
be used then switch to MAIN R5F0 with the appropriate interrupt numbers.

Let me know if you are unblocked & can resolve this,

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

Sorry for the delayed response.
1. We tried to run the CSL baremetal application on EVM and after choosing correct core and specific UART we were able to see the prints and interrupts.
The baremetal application runs fine. The Efuse values are also seen to be zero .Following prints are seen:

efuse 0 is : 0x0

efuse 1 is : 0x0

efuse 2 is : 0x0

efuse 3 is : 0x0

N40 error is : 0

P30 error is : 0

P125 err is : 0

P150 err is : 0

sensor id : 0 adc_code : 356 temp in milli degree celcius : 55110

sensor id : 1 adc_code : 359 temp in milli degree celcius : 55800

sensor id : 2 adc_code : 358 temp in milli degree celcius : 55570

sensor id : 3 adc_code : 362 temp in milli degree celcius : 56488

sensor id : 4 adc_code : 355 temp in milli degree celcius : 54880

Threshold values programmed in milli degree celsius are

lt_thr0_val : 56988 gt_thr1_val : 58788 gt_thr2_val : 60588

s0_temp: 55570 s1_temp: 55800 s2_temp: 56030 s3_temp: 57173 s4_temp: 55800
s0_temp: 56259 s1_temp: 56488 s2_temp: 56488 s3_temp: 57173 s4_temp: 55570
s0_temp: 56030 s1_temp: 56030 s2_temp: 55800 s3_temp: 56945 s4_temp: 55800
s0_temp: 56030 s1_temp: 56259 s2_temp: 56945 s3_temp: 57173 s4_temp: 56259
s0_temp: 55570 s1_temp: 56030 s2_temp: 56030 s3_temp: 57629 s4_temp: 56030
s0_temp: 56030 s1_temp: 56259 s2_temp: 56259 s3_temp: 57401 s4_temp: 56030
s0_temp: 56030 s1_temp: 56716 s2_temp: 56945 s3_temp: 57629 s4_temp: 56259
s0_temp: 56030 s1_temp: 56945 s2_temp: 56716 s3_temp: 57856 s4_temp: 56716
s0_temp: 57173 s1_temp: 56945 s2_temp: 57173 s3_temp: 57856 s4_temp: 55800
s0_temp: 56716 s1_temp: 56716 s2_temp: 56716 s3_temp: 57856 s4_temp: 55800

got gtThr1 interrupt

Crossed threshold 58788 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 56988

System running at a safe temperature

s0_temp: 55800 s1_temp: 56716 s2_temp: 56945 s3_temp: 58311 s4_temp: 56488

2. In order to register the interrupt from the MAIN domain we changed the interrupt numbers to 327,328,329 as you suggested to try.
Due to this change the application doesn't hang but still there are no interrupts seen.

As you have mentioned earlier, that the CSL library is exclusively written for MCU R5F but we need this feature in our stress test application in vision_apps.
Is it possible to enable MCU R5F core in vision_apps. So that we can compile the temperature alert feature along with our stress test application.
If yes, can you provide some guidelines to do so.

Thanks,

Dipti Natu

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

efuse 0 is : 0x0

efuse 1 is : 0x0

efuse 2 is : 0x0

efuse 3 is : 0x0

N40 error is : 0

P30 error is : 0

P125 err is : 0

P150 err is : 0

sensor id : 0 adc_code : 356 temp in milli degree celcius : 55110

sensor id : 1 adc_code : 359 temp in milli degree celcius : 55800

sensor id : 2 adc_code : 358 temp in milli degree celcius : 55570

sensor id : 3 adc_code : 362 temp in milli degree celcius : 56488

sensor id : 4 adc_code : 355 temp in milli degree celcius : 54880

Threshold values programmed in milli degree celsius are

lt_thr0_val : 56988 gt_thr1_val : 58788 gt_thr2_val : 60588

got gtThr1 interrupt

Crossed threshold 58788 System should take action to implement system cooling

got ltThr0 interrupt

System at a temperature below the threshold of 56988

System running at a safe temperature

s0_temp: 55800 s1_temp: 56716 s2_temp: 56945 s3_temp: 58311 s4_temp: 56488

As you have mentioned earlier, that the CSL library is exclusively written for MCU R5F. And we need this feature in our stress test application in vision_apps.
Is it possible to enable MCU R5F core in vision_apps. So that we can compile the temperature alert feature along with our stress test application.
If yes, can you provide some guidelines to do so.

Thanks,

Dipti Natu

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Dipti,

No issues. Wishing you a very happy new year.

Could you please paste the logs when you tried on Main Domain MCU?

I will try to look at the first.

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

Wishing you a great year ahead.

Please find the required log attached : TDA4_IntrNum_327_328_329.txt

Here the thresholds were set to 52, 54 and 56 degree Celsius and the interrupt numbers are set to 327, 328 and 329.

Thanks,

Dipti Natu

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hello Keerthy,

We just tried an experiment with R5F core to enable it and use it along with our application.

In order to enable MCU R5F core, following changes were made :

1. In file vision_apps\vision_apps_build_flags.mak : BUILD_CPU_MCU1_0?=yes

2. In file vision_apps\apps\basic_demos\app_tirtos\common\app_cfg.h : Uncommented #define ENABLE_IPC_MCU1_0

3. In file vision_apps\apps\basic_demos\app_tirtos\common\app_cfg_mcu1_0.h : Uncommented #undef ENABLE_TIOVX(This change doesn't affect the logs seen)

Observation :

1. In remote log no prints can be seen from MCU1_0. The log is attached for reference :

Fullscreen MCU1_0_enable_log.log Download

=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2021.01.06 15:16:07 =~=~=~=~=~=~=~=~=~=~=~=
`
U-Boot SPL 2019.01-00005-g29c2781fee (Jan 21 2020 - 18:50:05 +0900)
SYSFW ABI: 2.9 (firmware rev 0x0013 '19.12.1-v2019.12a (Terrific Lla')
Reading on-board EEPROM at 0x50 failed 1
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41ca13dc register: 0x23!
Trying to boot from MMC2
i2c_write: error waiting for data ACK (status=0x116)
read error from device: 41ca13dc register: 0x23!
Loading Environment from MMC... *** Warning - No MMC card found, using default environment

** File not found /lib/firmware/j7-main-r5f0_0-fw **
** File not found /lib/firmware/j7-mcu-r5f0_0-fw **
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.1(release):ti2019.04-rc1
NOTICE:  BL31: Built : 12:46:22, Nov 18 2019
I/TC: 
I/TC: OP-TEE version: ti2019.02 #1 2019. 11. 18. (월) 03:45:57 UTC aarch64
I/TC: Initialized

U-Boot SPL 2019.01-00005-gb84b6473df-dirty (Jan 21 2020 - 19:58:46 +0900)
Reading on-board EEPROM at 0x50 failed 1
Trying to boot from MMC2


U-Boot 2019.01-00005-gb84b6473df-dirty (Jan 21 2020 - 20:20:15 +0900)

Model: Texas Instruments K3 J721E SoC
DRAM:  4 GiB
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment

In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Reading on-board EEPROM at 0x50 failed 1
Net:   Could not get PHY for ethernet@046000000: addr 0
phy_connect() failed
eth-1: ethernet@046000000
Hit any key to stop autoboot:  2  1  0 
** Unable to read file /lib/firmware/j7-main-r5f0_0-fw **
** Unable to read file /lib/firmware/j7-main-r5f0_1-fw **
** Unable to read file /lib/firmware/j7-main-r5f1_0-fw **
** Unable to read file /lib/firmware/j7-c66_0-fw **
** Unable to read file /lib/firmware/j7-c66_1-fw **
** Unable to read file /lib/firmware/j7-c71_0-fw **
19856400 bytes read in 825 ms (23 MiB/s)
## Starting application at 0x80080000 ...
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Filesystem already exist!!
Starting MMC/SD memory card driver... SD
ethernet driver start
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
main: this fixed by sungwpark at last
setting env variables.
# 

# 

# 

# flashctl -p /dev/fs0 -e

# dd if=/sd/sbl/sbl_cust_img_mcu1_0_release.tiimage of=/dev/fs0p0 bs=32k

6+1 records in
6+1 records out
# dd if=/sd/sbl/sysfw.bin of=/dev/fs0p0 bs=32k seek=1 obs=512k

8+1 records in
0+1 records out
# dd if=/sd/sbl/can_boot_app_mcu_rtos_mcu1_0_release_ospi.appimage of=/dev/fs0p0 bs=32k seek=1 obs=1024k

6+1 records in
0+1 records out
# dd if=/sd/sbl/atf_optee.appimage of=/dev/fs0p0 bs=32k seek=1 obs=1536k

12+1 records in
0+1 records out
# dd if=/sd/sbl/ifs_qnx_vpu1_vp.appimage of=/dev/fs0p0 bs=32k seek=1 obs=4096k

707+1 records in
5+1 records out
# dd if=/sd/sbl/lateapp1 of=/dev/fs0p0 bs=32k seek=1 obs=39936k

148+1 records in
0+1 records out
# dd if=/sd/sbl/lateapp2 of=/dev/fs0p0 bs=32k seek=1 obs=47104k

187+1 records in
0+1 records out
# 

# 

# 

# NOTICE:  BL31: v2.2(release):ti2020.00
NOTICE:  BL31: Built : 23:55:51, Jan  5 2021
I/TC: 
I/TC: OP-TEE version: ti2020.00 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Tue Jan  5 18:26:09 UTC 2021 aarch64
I/TC: Initialized
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Starting MMC/SD memory card driver... SD
ethernet driver start
j7ospi_phy_config: tx/rd delay = 1f
Mailbox_plugInterrupt: interrupt Number 507, arg 0x1011EB78
j7ospi_phy_config: tx/rd delay = 88
Mailbox_plugInterrupt: interrupt Number 508, arg 0x1011ED10
Mailbox_plugInterrupt: interrupt Number 509, arg 0x1011EEA8
Mailbox_plugInterrupt: interrupt Number 510, arg 0x1011F040
Mailbox_plugInterrupt: interrupt Number 511, arg 0x1011F1D8
Starting TI IPC Resmgr
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
on: No such file or directory (./fs/SwUpdate)
Unable to access "/dev/fs0p1" (2)
filesystem create done
sh: /fs/startup.sh: No such file or directory
setting env variables.
# j7ospi_phy_config: tx/rd delay = 1f
j7ospi_phy_config: tx/rd delay = 87


# 

# 

# 

# mount -tdos -oexe=all /dev/sd0t12 /sd

# cp -r /sd/sbl/fs ./

# shutdown

Killed 
NOTICE:  BL31: v2.2(release):ti2020.00
NOTICE:  BL31: Built : 23:55:51, Jan  5 2021
I/TC: 
I/TC: OP-TEE version: ti2020.00 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Tue Jan  5 18:26:09 UTC 2021 aarch64
I/TC: Initialized
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Loading IFS...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040252000 kern:ffffff8040251000
Starting next program at vffffff8060085ae0
MMFLAGS=1
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.0 on TI J721E EVM Board!!
start serial driver
Starting MMC/SD memory card driver... OSPI
Starting MMC/SD memory card driver... SD
j7ospi_phy_config: tx/rd delay = 1f
j7ospi_phy_configMailbox_plugInterrupt: interrupt Number 507, arg 0x1011EB78
: tx/rd delethernet driver start
ay = 87
Mailbox_plugInterrupt: interrupt Number 508, arg 0x1011ED10
Mailbox_plugInterrupt: interrupt Number 509, arg 0x1011EEA8
Mailbox_plugInterrupt: interrupt Number 510, arg 0x1011F040
Mailbox_plugInterrupt: interrupt Number 511, arg 0x1011F1D8
Starting TI IPC Resmgr
kern.mbuf.nmbclusters: 8192 -> 262114
ethernet setting end
src/MCU/McuUpdateHandler.c:messageReceiver:467(): INFO: Wait for MCU connection.
Filesystem already exist!!
/fs/startup.sh[2]: 
: cannot execute - No such file or directory
startup.sh start!!

/fs/startup.sh[4]: 
: cannot execute - No such file or directory
Malformed integer '4
'
mount: Can't mount /sd
 (type dos) 
mount: Possible reason: No such file or directory 
/fs/startup.sh[7]: 
: cannot execute - No such file or directory
/fs/startup.sh[8]: cd: /fs/bin
 - No such file or directory
/fs/startup.sh[9]: ./shmemallocator
: cannot execute - No such file or directory
/fs/startup.sh[10]: 
: cannot execute - No such file or directory
/fs/startup.sh[11]: cd: /fs/ph00
 - No such file or directory
/fs/startup.sh[12]: ./LogFlushDaemon
: cannot execute - No such file or directory
/fs/startup.sh[13]: ./TimebaseEngine
: cannot execute - No such file or directory
setting env variables.
# 

# 

# 

# cd fs/bin

# ./shmemallocator

# ./vx_app_qnx_arm_remote_log.out &

[1] 245779
[MCU2_0]     47.209052 s: CIO: Init ... Done !!!

[MCU2_0]     47.209120 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU2_0]     47.209162 s: APP: Init ... !!!

[MCU2_0]     47.209181 s: SCICLIENT: Init ... !!!

[MCU2_0]     47.209266 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU2_0]     47.209305 s: SCICLIENT: DMSC FW revision 0x14  

[MCU2_0]     47.209330 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU2_0]     47.209353 s: SCICLIENT: Init ... Done !!!

[MCU2_0]     47.209373 s: UDMA: Init ... !!!

[MCU2_0]     47.210296 s: UDMA: Init ... Done !!!

[MCU2_0]     47.210347 s: MEM: Init ... !!!

[MCU2_0]     47.210381 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2800000 of size 16777216 bytes !!!

[MCU2_0]     47.210437 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 67108864 bytes !!!

[MCU2_0]     47.210482 s: MEM: Init ... Done !!!

[MCU2_0]     47.210501 s: FVID2: Init ... !!!

[MCU2_0]     47.210551 s: FVID2: Init ... Done !!!

[MCU2_0]     47.210575 s: VHWA: Init ... !!!

[MCU2_0]     47.210593 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2

[MCU2_0]     47.210741 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     47.210771 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2

[MCU2_0]     47.210912 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     47.210937 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2

[MCU2_0]     47.211050 s: SCICLIENT: Sciclient_pmSetModuleState success

[MCU2_0]     47.211074 s: VHWA: DOF Init ... !!!

[MCU2_0]     47.214857 s: VHWA: DOF Init ... Done !!!

[MCU2_0]     47.214910 s: VHWA: LDC Init ... !!!

[MCU2_0]     47.216949 s: VHWA: LDC Init ... Done !!!

[MCU2_0]     47.217001 s: VHWA: MSC Init ... !!!

[MCU2_0]     47.223248 s: VHWA: MSC Init ... Done !!!

[MCU2_0]     47.223301 s: VHWA: NF Init ... !!!

[MCU2_0]     47.224399 s: VHWA: NF Init ... Done !!!

[MCU2_0]     47.224447 s: VHWA: SDE Init ... !!!

[MCU2_0]     47.226039 s: VHWA: SDE Init ... Done !!!

[MCU2_0]     47.226092 s: VHWA: VISS Init ... !!!

[MCU2_0]     47.231269 s: VHWA: VISS Init ... Done !!!

[MCU2_0]     47.231326 s: VHWA: VDEC Init ... !!!

[MCU2_0]     47.271402 s: VHWA: VDEC Init ... Done !!!

[MCU2_0]     47.271718 s: VHWA: VENC Init ... !!!

[MCU2_0]     47.319879 s: VHWA: VENC Init ... Done !!!

[MCU2_0]     47.319938 s: VHWA: Init ... Done !!!

[MCU2_0]     47.319966 s: IPC: Init ... !!!

[MCU2_0]     47.319998 s: IPC: 8 CPUs participating in IPC !!!

[MCU2_0]     47.327468 s: IPC: Init ... Done !!!

[MCU2_0]     47.327531 s: APP: Syncing with 7 CPUs ... !!!

[MCU3_0]     47.232287 s: CIO: Init ... Done !!!

[MCU3_0]     47.232374 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU3_0]     47.232421 s: APP: Init ... !!!

[MCU3_0]     47.232444 s: SCICLIENT: Init ... !!!

[MCU3_0]     47.232537 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU3_0]     47.232572 s: SCICLIENT: DMSC FW revision 0x14  

[MCU3_0]     47.232595 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU3_0]     47.232619 s: SCICLIENT: Init ... Done !!!

[MCU3_0]     47.232641 s: MEM: Init ... !!!

[MCU3_0]     47.232673 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!!

[MCU3_0]     47.232725 s: MEM: Init ... Done !!!

[MCU3_0]     47.232744 s: IPC: Init ... !!!

[MCU3_0]     47.232777 s: IPC: 8 CPUs participating in IPC !!!

[MCU3_0]     47.254934 s: IPC: Init ... Done !!!

[MCU3_0]     47.255175 s: APP: Syncing with 7 CPUs ... !!!

[MCU3_1]     47.233454 s: CIO: Init ... Done !!!

[MCU3_1]     47.233537 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[MCU3_1]     47.233585 s: APP: Init ... !!!

[MCU3_1]     47.233604 s: SCICLIENT: Init ... !!!

[MCU3_1]     47.233696 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[MCU3_1]     47.233731 s: SCICLIENT: DMSC FW revision 0x14  

[MCU3_1]     47.233755 s: SCICLIENT: DMSC FW ABI revision 3.0

[MCU3_1]     47.233779 s: SCICLIENT: Init ... Done !!!

[MCU3_1]     47.233799 s: MEM: Init ... !!!

[MCU3_1]     47.233831 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!!

[MCU3_1]     47.233886 s: MEM: Init ... Done !!!

[MCU3_1]     47.233910 s: IPC: Init ... !!!

[MCU3_1]     47.233943 s: IPC: 8 CPUs participating in IPC !!!

[MCU3_1]     47.259039 s: IPC: Init ... Done !!!

[MCU3_1]     47.259262 s: APP: Syncing with 7 CPUs ... !!!

[C6x_1 ]     47.270576 s: CIO: Init ... Done !!!

[C6x_1 ]     47.270821 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>

[C6x_1 ]     47.270851 s: APP: Init ... !!!

[C6x_1 ]     47.270872 s: SCICLIENT: Init ... !!!

[C6x_1 ]     47.271058 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C6x_1 ]     47.271088 s: SCICLIENT: DMSC FW revision 0x14  

[C6x_1 ]     47.271109 s: SCICLIENT: DMSC FW ABI revision 3.0

[C6x_1 ]     47.271131 s: SCICLIENT: Init ... Done !!!

[C6x_1 ]     47.271148 s: UDMA: Init ... !!!

[C6x_1 ]     47.272607 s: UDMA: Init ... Done !!!

[C6x_1 ]     47.272634 s: MEM: Init ... !!!

[C6x_1 ]     47.272648 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!

[C6x_1 ]     47.272666 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_1 ]     47.272682 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!

[C6x_1 ]     47.272698 s: MEM: Init ... Done !!!

[C6x_1 ]     47.272706 s: IPC: Init ... !!!

[C6x_1 ]     47.272719 s: IPC: 8 CPUs participating in IPC !!!

[C6x_1 ]     47.279667 s: IPC: Init ... Done !!!

[C6x_1 ]     47.279696 s: APP: Syncing with 7 CPUs ... !!!

[C6x_2 ]     47.271949 s: CIO: Init ... Done !!!

[C6x_2 ]     47.271982 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>

[C6x_2 ]     47.271996 s: APP: Init ... !!!

[C6x_2 ]     47.272003 s: SCICLIENT: Init ... !!!

[C6x_2 ]     47.272086 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C6x_2 ]     47.272098 s: SCICLIENT: DMSC FW revision 0x14  

[C6x_2 ]     47.272107 s: SCICLIENT: DMSC FW ABI revision 3.0

[C6x_2 ]     47.272117 s: SCICLIENT: Init ... Done !!!

[C6x_2 ]     47.272126 s: UDMA: Init ... !!!

[C6x_2 ]     47.273213 s: UDMA: Init ... Done !!!

[C6x_2 ]     47.273239 s: MEM: Init ... !!!

[C6x_2 ]     47.273252 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!

[C6x_2 ]     47.273269 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!

[C6x_2 ]     47.273285 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!

[C6x_2 ]     47.273301 s: MEM: Init ... Done !!!

[C6x_2 ]     47.273310 s: IPC: Init ... !!!

[C6x_2 ]     47.273323 s: IPC: 8 CPUs participating in IPC !!!

[C6x_2 ]     47.280056 s: IPC: Init ... Done !!!

[C6x_2 ]     47.280086 s: APP: Syncing with 7 CPUs ... !!!

[C7x_1 ]     47.278737 s: CIO: Init ... Done !!!

[C7x_1 ]     47.278773 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>

[C7x_1 ]     47.278798 s: APP: Init ... !!!

[C7x_1 ]     47.278809 s: SCICLIENT: Init ... !!!

[C7x_1 ]     47.278873 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]

[C7x_1 ]     47.278889 s: SCICLIENT: DMSC FW revision 0x14  

[C7x_1 ]     47.278902 s: SCICLIENT: DMSC FW ABI revision 3.0

[C7x_1 ]     47.278915 s: SCICLIENT: Init ... Done !!!

[C7x_1 ]     47.278925 s: UDMA: Init ... !!!

[C7x_1 ]     47.279050 s: UDMA: Init ... Done !!!

[C7x_1 ]     47.279063 s: MEM: Init ... !!!

[C7x_1 ]     47.279076 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!

[C7x_1 ]     47.279100 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!

[C7x_1 ]     47.279122 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!

[C7x_1 ]     47.279140 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!

[C7x_1 ]     47.279158 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 251658240 bytes !!!

[C7x_1 ]     47.279177 s: MEM: Init ... Done !!!

[C7x_1 ]     47.279186 s: IPC: Init ... !!!

[C7x_1 ]     47.279198 s: IPC: 8 CPUs participating in IPC !!!

[C7x_1 ]     47.281732 s: IPC: Init ... Done !!!

[C7x_1 ]     47.281746 s: APP: Syncing with 7 CPUs ... !!!

#

2. When our application is run, following error is seen :

In app_init...
88.235635 s: VX_ZONE_ERROR:[ownContextCreateCmdObj:161] context object descriptor [0] allocation failed
88.235668 s: VX_ZONE_ERROR:[vxCreateContext:895] context objection creation failed
88.235699 s: VX_ZONE_ERROR:[vxSetReferenceName:646] Invalid reference

Process 249876 (vx_app_stress_test.out) terminated SIGSEGV code=1 fltno=11 ip=00000000100f6764(/fs/bin/./vx_app_stress_test.out@vxGetObjectArrayItem+0x0000000000000014) mapaddr=000000000002e764. ref=0000000000000098
Memory fault (core dumped)

Thanks,

Dipti

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Dipti,

I have got the thermal alerts CSL working on Main R5F0. Interrupt routing is a bit more complicated on Main R5F side.
I will clean up the code & share that by tomorrow.

Best Regards,
Keerthy

0 Keerthy J over 4 years ago in reply to Keerthy J

TI__Guru**** 164680 points

Hi Dipti,

Attaching the patch on top of csl folder of 7.0 SDK.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_vtm_5F00_pvt_5F00_sensor_5F00_temp_5F00_alert_2D00_Port_2D00_Main_2D00_domain_2D00_R5F0_2D00_aka_2D00_.patch

Please resolve this thread as it solves your original question of alert monitoring on Main domain R5F.

Best Regards,
Keerthy

0 Dipti Natu over 4 years ago in reply to Keerthy J

Intellectual 700 points

Hi Keerthy,

Thank you for providing this solution.

We applied the patch that you have provided. I took the changes in my application. The application runs fine and we are able to see alerts.

We will now test this application for longer durations and various scenarios.

Basic application works well. Thank you for your co-operation.

Thanks,

Dipti

0 Keerthy J over 4 years ago in reply to Dipti Natu

TI__Guru**** 164680 points

Hi Dipti,

Please resolve this when you are done testing.

Best Regards,
Keerthy

Processors

Processors forum

PROCESSOR-SDK-DRA8X-TDA4X: Thermal shutdown alerts and interrupts