CCS/TMS320C6748: c6748 Universal parallel port internal and external loopback is not working?

Ramachandra Parlapalli

Part Number: TMS320C6748

Tool/software: Code Composer Studio

Hi sir,

i am using TMS320C6748 DSP through Universal Parallel Port FPGA(ARTIX) Connected.

In DSP C6748 internal loop back of universal parallel port below code used not worked? for external data transfer also not happening?

For internal loop back:

#define PINMUX_13_REG (13)
#define PINMUX_13_MASK (0xFFFF00FF)
#define PINMUX_13_VAL (0x44440011) //UPP_CHA_WAIT,UPP_CHA_ENABLE,UPP_CHA_START,UPP_CHA_CLOCK,-,-,CLKOUT,RSTOUT

#define PINMUX_14_REG (14)
#define PINMUX_14_MASK (0xFFFFFFFF) //GP6[6]
#define PINMUX_14_VAL (0x44444481) //DSP-FPGA-GPIO1,DSP-FPGA-CLKIN0

#define PINMUX_15_REG (15)
#define PINMUX_15_MASK (0xFFFFFFFF)
#define PINMUX_15_VAL (0x44444444) //UPP_DATA[2:9]

#define PINMUX_16_REG (16)
#define PINMUX_16_MASK (0x000000FF)
#define PINMUX_16_VAL (0x00000044) //UPP_DATA[0:1]

#define PINMUX_17_REG (17)
#define PINMUX_17_MASK (0xFFFFFF00)
#define PINMUX_17_VAL (0x00000000) //BOOT[2-7]

#define PINMUX_18_REG (18)
#define PINMUX_18_MASK (0x00FFFFFF)
#define PINMUX_18_VAL (0x00444400) //UPP_CHB_WAIT,UPP_CHB_ENABLE,UPP_CHB_START,UPP_CHB_CLOCK,BOOT[0-1]

main()

{

upp_config_t config;
UPXS2_t * UPIS2r = (UPXS2_t *)&(UPP->UPIS2);
UPXS2_t * UPQS2r = (UPXS2_t *)&(UPP->UPQS2);

uint32_t retVal = ERR_NO_ERROR;
uint32_t i;

UPP_init(&config);
//UPCTL
config.UPCTL.value=0;
config.UPCTL.bits.IWB = 1; //8-bit interface //16 bit interface
config.UPCTL.bits.DPWB = 0; //8-bit interface//10 bit data

config.UPCTL.bits.DPFA = 0;
config.UPCTL.bits.DPWA = 0; //8-bit interface//10 bit data
config.UPCTL.bits.IWA = 1; //8-bit interface//16 bit interface

config.UPCTL.bits.CHN = 1; //dual channel mode
config.UPCTL.bits.MODE = 2; //0 all recv, 1 all xmit, 2 a recv b xmit, 3 a xmit b recv
//Channel A FPGA, Channel B FPGA

//UPICR
config.UPICR.value=0;
config.UPICR.bits.CLKDIVB = 0; //Set FPGA sampling freqency at 75 Mhz

//UPIVR
config.UPIVR.value=0;
config.UPIVR.bits.VALB = 0x1000;
config.UPIVR.bits.VALA = 0x0000;

//UPTCR
config.UPTCR.value=0; //all values 0 for 64byte DMA bursts read / write
//UPDLB
config.UPDLB.value=0x0200; //loopback
//UPIES
config.UPIES.value=0; //dont enable any interrupts
//UPPCR
config.UPPCR.value = 0;
config.UPPCR.bits.EN = 1; //enable uPP
config.UPPCR.bits.RTEMU = 1; //allow emulator use
config.UPPCR.bits.SOFT = 1; //allow emulation

// UPP_init(&config);

UART_txString(DEBUG_PORT,"\n\r---Generating 73.2421875KHz sine wave for 20 seconds---\r\n\r\n");
for(i = 1; i < 1464843; i++)
{

UPP->UPQD0 = (uint32_t)&xmit_buffer;//add next DMA transfer
UPP->UPQD1 = 0x00010080; //1 lines 128 bytes per line
UPP->UPQD2 = 0x00000080; //no offset between lines

while(UPQS2r->bits.PEND == 1){};
}

UART_txString(DEBUG_PORT,"---Collecting 64 samples from ADC---\r\n");
UPP->UPID0 = (uint32_t)&recv_buffer;//add next DMA transfer
UPP->UPID1 = 0x00010080; //1 lines 128 bytes per line
UPP->UPID2 = 0x00000080; //no offset between lines
while(UPIS2r->bits.PEND == 1){};

UART_txString(DEBUG_PORT,"---Displaying collected samples---\r\n");
for(i = 0; i < 1464843; i++)
{
UPP->UPQD0 = (uint32_t)&recv_buffer;//add next DMA transfer
UPP->UPQD1 = 0x00010080; //1 lines 128 bytes per line
UPP->UPQD2 = 0x00000080; //no offset between lines

while(UPQS2r->bits.PEND == 1){}; //wait for tx transfer to complete
}

return retVal;

}

uint32_t UPP_init(upp_config_t * config)
{
uint32_t rtn = ERR_INIT_FAIL;
uint32_t i = 0;

EVMC6748_lpscTransition(PSC1, DOMAIN0, LPSC_UPP, PSC_ENABLE); //Provide power to uPP

//reset uPP
SETBIT(UPP->UPPCR, UPP_UPPCR_SWRST);
for(i = 0; i < 300; i++){}; //wait 200 clock cycles for reset.
CLRBIT(UPP->UPPCR, UPP_UPPCR_SWRST);

//setup control registers
UPP->UPCTL=config->UPCTL.value;
UPP->UPICR=config->UPICR.value;
UPP->UPIVR=config->UPIVR.value;
UPP->UPTCR=config->UPTCR.value;
UPP->UPDLB=config->UPDLB.value;
UPP->UPIES=config->UPIES.value;
UPP->UPPCR=config->UPPCR.value;

return (rtn);
}

As per pinmux everything configured properly.

For external loopack (DSPC6748---->ARTIX FPGA)