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66AK2G12: Interrupt Latency for 66AK2G12

Krishna Boopathy J
Intellectual 340 points

Part Number: 66AK2G12
Other Parts Discussed in Thread: SYSBIOS

Hi,

We are using the 66AK2G12 processor and running TI-RTOS on the ARM core.

For our application we are using several GPIO interrupts and for one such interrupt we require very less latency time. But during testing we observe various interrupt latency times on every test iteration. For registering the interrupts we aer using the HwiP drivers.

On one test iteration we are observing 15uSec latency and for another iteration we were able to get 80uSec latency. 

So can you help me with the following queries:

1. Can I use zero latency interrupts in K2G processor for the ARM core. If possible can you refer any example projects if available.

2. Please suggest any other techniques to reduce the interrupt latency time and to maintain a constant interrupt latency,

Thanks,

Krishna.

  • 0
    TI__Guru** 116950 points

    All examples in TI Processor SDK RTOS for the device are using IRQ on the A15 and not FIQ. The lowest possible interrupt latency with this is provided in the TI RTOS benchmarks here:

    bios_6_76_02_02\packages\ti\sysbios\benchmarks\doc-files\GCC_A15F_ti_platforms_evmDRA7XX_time.html

    the only other option that I know to get low and constant interrupt latency with this device is using the ICSS PRU GPIO pin and code to handle such interrupts.

    Regards,

    Rahul 

  • 0 in reply to Rahul Prabhu
    Intellectual 340 points

    Hi Rahul,

    We are registering the interrupt using HwiP drivers. while registering an interrupt for the triggerSensitivity we use the option "OSAL_ARM_GIC_TRIG_TYPE_EDGE" from the following available types.

    typedef enum
{

/**< Corresponding interrupt is level-sensitive */
OSAL_ARM_GIC_TRIG_TYPE_LEVEL = 1,

/**< Corresponding interrupt is edge */
OSAL_ARM_GIC_TRIG_TYPE_EDGE = 2,

/**< Coressponding interrupt is high level sensitive */
OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL = 3,

/**< Coressponding interrupt is low level sensitive */
OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL = 4,

/**< Coressponding interrupt is rising edge sensitive */
OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE = 5,

/**< Coressponding interrupt is falling edge sensitive */
OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE = 6

} OSAL_armGicTrigType_t;

    Here when we try to change it to "OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE" the interrupt is not getting triggered. But meanwhile "OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE" is working fine.

    So please help us to configure the interrupt in "OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE" mode.

    Thanks,

    Krishna.