I'm trying to get the PCF8563 real time clock (which by the way has code to access the I2C). However, as soon as the I2C is enabled it becomes busy. I tried writing the busy bit in the DAVINCI_I2C_STR_REG (2nd to last line) to clear it but it doesn't seem to clear as shown by the last line (0x1000 is the busy bit). I've gone into code composer debugger and looked at the registers. Right out of reset I can see the problem. Initially BB in ICSTR is clear. Then if I enable I2C0 in the pin mux and take the I2C out of reset by setting IRS in ICMDR high the BB in ICSTR goes high. Another oddity is that ICPDIN shows that PDIN0 (scl) is low even though I can see on the oscilloscope it's high. This happens to be one of the conditions for setting the busy bit. But the text shows that IRS must be low to cause this too. I know I'm on the right pins because if I set it up as GPIO I can toggle it high and low. This is not on the EVM. It is a custom board. But it seems like there is a hardware problem with the I2C0. Has anybody been able to get it to work correctly. Below are debug messages I put in Linux. This may belong in a different forum. But I initially started from Linux.
reg = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
reg |=(DAVINCI_I2C_STR_BB | DAVINCI_I2C_STR_ARDY); //clear busy bit
davinci_i2c_write_reg(dev,DAVINCI_I2C_STR_REG, reg);
reg = davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG);
Reading I2C register @ 0xfec22000 register 0x00000024 value = 0x00000000
Writing I2C register @ 0xfec22000 register 0x00000024 data=0x00000020
Writing I2C register @ 0xfec22000 register 0x00000004 data=0x00000067
Reading I2C register @ 0xfec22000 register 0x00000008 value = 0x00001410
Writing I2C register @ 0xfec22000 register 0x00000008 data=0x00001414
Reading I2C register @ 0xfec22000 register 0x00000008 value = 0x00001410
These debug messages were generated from:
static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
int reg, u16 val)
{
pr_warning("Writing I2C register @ 0x%08x register 0x%08x data=0x%08x \n",(u32)i2c_dev->base, reg, val);
__raw_writew(val, i2c_dev->base + reg);
}
static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
{
u32 readValue;
readValue = __raw_readw(i2c_dev->base + reg);
pr_warning("Reading I2C register @ 0x%08x register 0x%08x value = 0x%08x \n",(u32) i2c_dev->base,reg, readValue);
return (readValue);
}
from the user manual:
Bus busy bit. BB bit indicates whether the I2C-bus is busy or is free for another data transfer. In the
master mode, BB is controlled by the software.
0 Bus is free. BB is cleared by one of the following events:
• The I2C receives or transmits a STOP bit (bus free).
• BB is manually cleared. To clear this bit, write a 1 to it.
• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset).
1 Bus is busy. When the STT bit in ICMDR is set to 1, a restart condition is generated. BB is set by one of
the following events:
• The I2C has received or transmitted a START bit on the bus.
• I2Cx_SCL is in a low state and the IRS bit in ICMDR is 0.