AM4378: MII timing diagram

Sri Viswa Sathiamoorthy

Part Number: AM4378

Hi,

In our design, the AM4378 processor is interfaced(MII interface) with DP83620SQE/NOPB. I have performed timing calculation(calculation doesn't include delays due to PCB).

As per DP83620SQE/NOPB datasheet, the maximum data valid after RX_CLK clock rising edge is 30ns. The total clock period is 40ns. As per the AM4378 datasheet, the data(RXD[0:3]) is latched at the next rising edge of the RX_CLK. Hence, the setup time available is 40ns-30ns = 10ns. The required setup time of AM4378 is 8ns. The margin available is 2ns. Hence the setup time is passed.

Whether the timing calculation performed is correct?

Thanks

Viswa

over 4 years ago

0 Brad Griffis over 4 years ago

TI__Guru*** 125430 points

Yes, that's correct. The "max" time and the data period are used to figure out the setup time.

Similarly, the "min" time delay from the PHY coincides with the hold time requirement on the AM437x. The min delay time is 10ns, which exceeds the 8ns hold requirement of the AM437x.

I assume you've done these same checks on the TX side, though reversed, i.e. using the AM437x characteristics to match up against the PHY's requirements?

0 Sri Viswa Sathiamoorthy over 4 years ago in reply to Brad Griffis

Intellectual 290 points

Hi,

Thanks for you reply

Yes.

For TX:

The max data valid is 25ns. The available setup time is 15ns. The requirement is 10ns. The margin available is 5ns

For hold time, the minimum data valid is hold time which is 5ns. The requirement is 0ns. The margin available is 5ns

Is this correct?

Thanks

Viswa

0 Brad Griffis over 4 years ago in reply to Sri Viswa Sathiamoorthy

TI__Guru*** 125430 points

Correct.

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AM4378: MII timing diagram