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CCS/66AK2G12: Nesting/Pre-emptive Hwip in TI-RTOS

sudhanthiradasan R
Intellectual 565 points

Part Number: 66AK2G12
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

Hi,

We are using two Hwip interrupts with same priority in Arm a15 core.

In SYS/BIOS user guide i read

"Hardware interrupts are preempted by another interrupt unless interrupts are globally disabled or when specific interrupts are individually disabled."

and 

"* On some targets, hardware interrupts can be individually enabled and disabled. This is not true on all targets. Also, some targets have controllers that support hardware interrupt prioritization, in which case a Hwi can only be preempted by a higher-priority Hwi."

Even though we are using same priority for both interrupts, it seems like race condition occurs(a global variable used between these two ISRs). So can an interrupt with same prioirty pre-empt the other? If so how can we disable it?

  • 0
    TI__Guru** 116960 points

    On the C66x on K2G, the DSP has 12 interrupts with interrupt 12 from an architecture is treated as lower priority as compared to interrupt 1 which is the highest priority. I am not sure if A15 has anything setup in this way. You may want to check ARM documentation to see if that is the case.

    From sYSBIOS perspective when you setup HWIp, you may want to look at the MAsking optons available. 

    Setting the masking to  Hwi_MaskingOption_LOWER might help prevent any interrupt at same priority from causing this race condition as all interrupts with current or lower priority will be masked.

    Regards,

    Rahul