AM3358: Wait of the synchronous read/write access via GPMC on AM3358

Hi Nomo-san,

This restriction means that when using the GPMC CLK with divide-by-1 or divide-by-2 from the internal GPMC_FCLK, the WAIT signal must be valid (meeting setup time) at least 1 GPMC CLK cycle before WRITEACCESSTIME. It cannot change just before WRITEACCESSTIME. WAITMONITORINGTIME must be > 0.

When the GPMC CLK is using divide-by-3 or divide-by-4, the WAIT signal can become valid just before the same GPMC CLK cycle as WRITEACCESSTIME.

Can you confirm the writes and reads will be synchronous (ie. clock is used)? If asynchronous, then the WAIT signal must be valid 2 GPMC CLK cycles before WRITEACCESSTIME/READACCESSTIME for asynchronous transfers. If more time is requied from WAIT becoming valid to the WRITEACCESSTIME/READACCESSTIME, then WAITMONITORINGTIME can be increased.

I believe your 2 listed expectations will be satisfied.
AD multiplexing 16 bit mode - yes
While wait signal is asserted, GPMC_CLK output forever - You may want to implement a software timeout to detect when the WAIT signal is never released. If this happens the GPMC cycle should never end, so the CLK should not stop.

Will burst mode be used (WRITEMULTIPLE or READMULTIPLE set to 1)?

Regards,
Mark

Hi Mark-san,

Thank you for your reply and very helpful information.
We will use burst mode for both of RD/WR.
GPMC will be connected to FPGA, and burst access and single access will be changed by switching CS.
(Multiple CSs is connected to the same FPGA device.)

Best Regards,
Nomo

Hi Mark-san,

Thank you for your reply.
We'll check that WRITETYPE = 1, Write synchronous.

Best Regards,
Nomo