TDA2HG: Why DSS DDR Peak data much larger than average data

Hi Tim,

This might be  because display pipe is throttled by pixel clock, but m2m path is not. It will try process data as fast as possible.. so will increase peak BW.

Regards,

Brijesh 

Hi Brijes,

Thanks for your quick reply!

Since our system is limited by DDR bandwith, we must make sure every module works at reasonable bw. Much more larger peak data may block other modules.

If I want get smaller peak data, you mean I should slow down the m2m? Would you please tell me how to do it?

Thanks!

BR/Tim

Hi Tim,

I doubt that there is anyway to slow down the DSS M2M path, will double confirm the same.

You could probably disable mflag generation for this path, then it will automatically reduce the peak traffic.

Regards,

Brijesh

Hi Brijesh,

I doubt that there is anyway to slow down the DSS M2M path, will double confirm the same.

Thanks! I'll wait your confirm.

You could probably disable mflag generation for this path, then it will automatically reduce the peak traffic.

Sorry, I don't know where to disable M2M mflag. Only I found is "Utils_setDssMflagMode(UTILS_DSS_MFLAG_MODE_FORCE_ENABLE);" in "apps/src/rtos/common/chains_main_linux.c". But after I comment it, "Peak data" not be reduced.

BR/Tim

Hi Brijesh,

Any update?

Sorry for urge. Thanks!

BR/Tim

Hi Tim,

The only thing that i see in the DSS is to lower the the clock, You could use clock divisors to lower the clock. But i think this might affect your performance. Please see if this helps.

Regards,

Brijesh

Hi Tim,

The other way that i am thinking is, you could run in display + capture mode, in this case, capture ie write back output will be throttled at the pixel clock. So if you set the pixel clock lower, then pixels will also be read and written at lower speed.

Regards,

Brijesh

I was talking about value of LCD field in the DISPC_DIVISOR register..

Regards,

Brijesh

Hi Brijesh,

Sorry I'm not quite understand what you said.

The only thing that i see in the DSS is to lower the the clock, You could use clock divisors to lower the clock. 

So you mean use DISPC_DIVISOR register to slow down the pixel clock? But it may effcet display fps.

The other way that i am thinking is, you could run in display + capture mode, in this case, capture ie write back output will be throttled at the pixel clock

My visionSDK usecase link is :DispDistSrc_weston -> DssM2mWb-> Display_m4

DispDistSrc_weston is input rgb video from weston, then DssM2mWb will convert it to yuv, then Display_m4 will display it.

So I think it is samilar with what you said. Because Display_m4 is throttled at the pixel clock, if I set the pixel clock lower, then DssM2mWb will at lower speed also. Right?

Thanks!

BR/Tim

Hi Brijesh,

Actually GPU and MPU also have this problem. They boost up when frame come in. So is there any way to make all of their DDR bandwidth usage more smoothly.

Thanks for your help!

Hi Tim,

Not sure about the GPU.

There is an performance AppNote at . Could you please refer to it and see if it has information on throttling DSS & GPU?

Rgds,

Brijesh 

Hi Tim,

So you mean use DISPC_DIVISOR register to slow down the pixel clock? But it may effcet display fps.

Why will it affect fps? DISPC_DIVISOR will reduce clock for DSS and should slow down DSS M2M WB path also.

DSSM2MWB vs Display + Capture path are different..  Because Display + Capture path is controlled by final output pixel clock.. and DSS M2M WB path will run at DSS clock, not by any pixel clock..

Rgds,

Brijesh

Hi Brijesh,

So you mean configure the register below right?

Now we set it as 0x00010001. Would you please tell which value should I set?

Thanks for your help!

Hi Tim,

Yes, that's correct, can you try setting 0x00020001?

Rgds,

Brijesh

Hi Brijesh,

After I set it as 0x00020001, display shows below. Did some other registers should I configure also?

Anyway peak data is lower than 700MB/s.

Actually I hope we can smooth this wave like a straight line. For example, it rise and fall between 500MB/s.

Thanks!

BR/Tim

Hi Tim,

ok, so it is affecting the display. So lets revert it back to original value. 

Can you check what is the value of the field MFLAG_CTRL in DSS register? I want to see if it is set to value 0x2. If it is set to 0x2, can you try setting same threshold values for low and high for WB input path and WB output path? 

Rgds,

Brijesh 

Hi Brijesh,

Yes my MFLAG_CTRL is 0x2.

And I set DISPC_VID1_MFLAG_THRESHOLD, DISPC_VID2_MFLAG_THRESHOLD and DISPC_WB_MFLAG_THRESHOLD as 0x03000200. But peak data still higher than 1G/s.

Thanks!

BR/Tim

Hi Tim,

Do you mean DSS alone is generating such high peak? Can you please share more details? 

Regards,

Brijesh

Hi Brijesh,

Yes. I dump DSS access ddr data from file "links_fw/src/rtos/utils_common/src/utils_stat_collector.c" funciton "Utils_statCollectorTskMain" which get state collector counter registers every 5ms.

Please check these data below:

dss data.xlsx

Every data unit is MB/s

BR/Tim

Hi Tim,

Can you provide some more information?

1, How many video/graphics pipelines are active?

2, What is the resolution, fps and format on each pipeline? 

Essentially, lets check theoretically what's the BW requirement for DSS and see if it matches with the data captured.

Regards,

Brijesh 

Hi Brijesh,

1, How many video/graphics pipelines are active?

Output interface is vout1 and vencId is LCD1. 

And DssM2mWbLink inpipline is VID2, and it's input node is LCD2.

2, What is the resolution, fps and format on each pipeline? 

1920x720 display resolution, 20fps, Usecase link: qt->weston(rgb)->dssm2m(yuv422)->display. wb pipline convert rgb to yuv422 and vout1 send yuv422 over BT656.

So the theoretically BW should like below:

Hi Tim,

One more question, is the peak BW due to m2m path or due to display path? Can you please check it by disabling one of them and then checking BW again? 

Regards,

Brijesh

Hi Brijesh,

After I disabled display link(just "System_getLinksFullBuffers" and "System_putLinksEmptyBuffers"), which use Vout1 pipeline as output, DSS bandwidth drop a little but still jump to more than 900 MB/s.

Then I set DISPC_WB_MFLAG_THRESHOLD as 0x03000200, but it still more than 800 MB/s. I attached data: dss bandwidth.xlsx

Is threshold setting not valid? And can we conclude that most of bandwidth consumed by M2MWB?

Thanks!

BR/TIm

Hi Tim,

Threshold is just used in generating MFLAGs and so giving higher priority to the display.. What we want is to disable this mechanism, so that it does not generate instantaneous peak for the WB path. So can you set same thresholds for WB path and input path? 

Rgds,

Brijesh  

Hi Brijesh,

Threshold is just used in generating MFLAGs and so giving higher priority to the display.

This priority is only for DSS or every module(MPU, GPU, IPU, etc.)?

What we want is to disable this mechanism, so that it does not generate instantaneous peak for the WB path.

Why not just disable global MFLAG in register DISPC_GLOBAL_MFLAG_ATTRIBUTE as 0x0?

So can you set same thresholds for WB path and input path? 

Yes, I set DISPC_WB_MFLAG_THRESHOLD  and DISPC_VID2_MFLAG_THRESHOLD as 0x03000200 and still jump to 1GB/s sometimes.

Hi Tim,

This priority is only for DSS or every module(MPU, GPU, IPU, etc.)?

No, threshold based mechanism is for DSS

Why not just disable global MFLAG in register DISPC_GLOBAL_MFLAG_ATTRIBUTE as 0x0?

I guess you also have actual; display path, if you disable mflag completely, it would affect this path as well. 

Yes, I set DISPC_WB_MFLAG_THRESHOLD  and DISPC_VID2_MFLAG_THRESHOLD as 0x03000200 and still jump to 1GB/s sometimes.

can you set both the registers to 0x0?

Rgds,

Brijesh

Hi Brijesh,

No, threshold based mechanism is for DSS.

If this it only for DSS, and I only have VID1 and WB in used, I think the change of priority for WB effect nothing. Because, the VID1 only need about 80MB/s, the high or low priority of WB still have much bandwidth can be used. So I think it still will jump to 1GB/s.

I guess you also have actual; display path, if you disable mflag completely, it would affect this path as well. 

Actually I already tried it, and nothing changed.

can you set both the registers to 0x0?

The default value is 0. So nothing happend~

BR/Tim

Hi Tim,

If you stopped enqueueing buffer to the display, that does not stop the display.. It will still read last enqueeued buffer. What you need to do is to stop the display path itself.. It should not read from the memory at all.

You mentioned that the threshold values are set to 0x03000200, can you set them to 0x0 and check? 

Regards,

Brijesh

Hi Brijesh,

If you stopped enqueueing buffer to the display, that does not stop the display.

I never called FVID2_start, so I think FVID2 driver never run, right? If not, would you please tell me how to stop the display path itself?

You mentioned that the threshold values are set to 0x03000200, can you set them to 0x0 and check? 

Yes, I checked it still jump to 1GB/s.

BR/Tim

Hi Brijesh,

Any update?

BR/Tim

Hi Tim,

I am still trying to figure out if there is any other way to spread the traffic. I will get back to you as soon as possible. 

Regards,

Brijesh

Thanks Brijesh, and happy christmas!