Hi All,
I would like to ask a question on EMIFA pin multiplexing.

Please refer to the figure above. Why each of EM_D[0..7] is available from two pins? Is it intended to provide more flexibility to the user?
And if the user choose (2) as EMIFA data bus, then there is no pin available for VPBE output, since each of COUT[0..7] signal has only one pin associated. Then what can he do if he still want to communicate with EMIFA devices?
Does this mean if one choose (2), then he cannot use VPBE and EMIFA simultaneously?
But nor can he choose (1) as EMIFA data bus, since he will have difficulty with
1. EM_A[13..20] address pins
2. CCD[8..15] VPFE input pins
So why are these important pins all placed together and make it appear difficult to handle?
Zheng
