TDA4VM: HSDIV_CLKOUT Calculation formula Uncertain

xin alex

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA829,

hello,

In paper 《J721E DRA829/TDA4VM/AM752x Processors Silicon Revision 1.0》5.4.5.4.1.2.5 HSDIVIDER .

Table 5-2185: the HSDIVIDER output clock frequency is given by the equations "HSDIV_CLKOUT = FOUTP / (HSDIV + 1) "；
Figure 5-1019: HSDIV[0~4] input clock is FOUTPOSTDIV，HSDIV[5~9] input clock is FOUTP；

so equations in table 5-2185 don't match description in Figure 5-1019

Example: MAIN_PLL12_HSDIV0_CLKOUT (DDRSS0) , if I used FOUTP as input clock , MAIN_PLL12_HSDIV0_CLKOUT is 934.4MHz，but if I uses FOUTPOSTDIV as input clock , MAIN_PLL12_HSDIV0_CLKOUT is 467.2 MHz. （TDA4VM Evaluation Module, LINUX SDK 7.0.1）

I want to known whether input clock is always FOUTP When calculate HSDIV_CLKOUT in HSDIV[0 ~ 9] ?

thanks

over 5 years ago

0 Gaviraju Doddabettahalli Bettegowda over 5 years ago

TI__Genius 14305 points

Hi,

Can you attach the image again?

Thanks

Gaviraju

0 xin alex over 5 years ago in reply to Gaviraju Doddabettahalli Bettegowda

Intellectual 506 points

hello, attach the image.

in paper 《J721E DRA829/TDA4VM/AM752x Processors Silicon Revision 1.0》5.4.5.4.1.2.5 HSDIVIDER
The HSDIVIDER output clock frequency is given by the equations in Table 5-2185.

but in Figure 5-1019 ， HSDIV[0~4] input clock is FOUTPOSTDIV，so equations in table 5-2185 don't match description in Figure 5-1019

I want to known whether input clock is always FOUTP When calculate HSDIV_CLKOUT in HSDIV[0 ~ 9] ?

0 Gaviraju Doddabettahalli Bettegowda over 5 years ago in reply to xin alex

TI__Genius 14305 points

Still the image is not available to view

0 xin alex over 5 years ago in reply to Gaviraju Doddabettahalli Bettegowda

Intellectual 506 points

hi,

the image already inserted ,

thanks

0 Kevin Lavery over 5 years ago

TI__Mastermind 22270 points

Look into the CFG registers (e.g. MCU_PLL0_CFG or PLL1_CFG or …)

It defines the connection of the PLL to the HSDIV:

By definition HSDIV

[4:0] are connected the PLL FOUTVCO output clock and HSDIV

[15:5] are connected to the PLL FOUTPOSTDIV output clock

What this means is that for HSDIV numbered 4 or less, the divided clock is FOUTP; for HSDIV elements numbered 5 or greater, the input clock to the HSDIV is FOUTPOSTDIV. In either case, the divider is (HSDIV + 1).

Taking a random example, if you look at the C66x DSPSS Clocks and Resets Table (Table 6-574 in my doc), you will find that the C66 is clocked by MAIN_PLL13_HSDIV0_CLKOUT which means PLL13 through HSDIV0. Because the HSDIV is 4 or less, the clock it uses is FOUTP.

Best regards,

Kevin

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TDA4VM: HSDIV_CLKOUT Calculation formula Uncertain