Other Parts Discussed in Thread: OMAP3530
I have an fpga connected to the GPMC bus on an omap3530. One of the lines from the fpga is attached to a gpio. This gpio is configured to generate an interrupt that starts the data transfer from the FPGA. I have a logic analyzer monitoring the various signals and observe that it takes 5 micro seconds from the time the gpio goes high, indicating data available, to the ISR getting control and starting the transfer.
Does anyone have any ideas how I can reduce this delay?
Philip
